CS5345

30

6.3.1

Functional Mode (Bits 7:6)

Function:

Selects the required range of sample rates.

6.3.2

Digital Interface Format (Bit 4)

Function:

The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface For-

mat bit. The options are detailed in Table 6 and may be seen in Figure 3 and 4.

6.3.3

Mute (Bit 2)

Function:

When this bit is set, the serial audio output of the both channels will be muted.

6.3.4

High Pass Filter Freeze (Bit 1)

Function:

When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be

frozen and continue to be subtracted from the conversion result. See “High Pass Filter and DC Offset

Calibration” on page 22.

6.3.5

Master / Slave Mode (Bit 0)

Function:

This bit selects either master or slave operation for the serial audio port. Setting this bit will select mas-

ter mode, while clearing this bit will select slave mode.

6.4

MCLK Frequency - Address 05h

Table 5. Functional Mode Selection

FM1

FM0

Mode

0

0

Single-Speed Mode: 4 to 50 kHz sample rates

0

1

Double-Speed Mode: 50 to 100 kHz sample rates

1

0

Quad-Speed Mode: 100 to 200 kHz sample rates

11

Reserved

Table 6. Digital Interface Formats

DIF

Description

Format

Figure

0

Left Justified, up to 24-bit data (default)

0

3

1

14

76543

210

Reserved

MCLK

Freq2

MCLK

Freq1

MCLK

Freq0

Reserved

Reserved

Reserved

Reserved