CS5345 datasheet(31/39 Pages) CIRRUS

31 / 39 page

CS5345

6.4.1

Master Clock Dividers (Bits 6:4)

Function:

Sets the frequency of the supplied MCLK signal. See Table 7 below for the appropriate settings.

6.5

PGAOut Control - Address 06h

6.5.1

PGAOut Source Select (Bit 6)

Function:

This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to

Table 8 below.

6.6

Channel A PGA Control - Address 07h

6.6.1

Channel A PGA Gain (Bits 5:0)

Function:

See “Channel B PGA Gain (Bits 5:0)” on page 31.

6.7

Channel B PGA Control - Address 08h

6.7.1

Channel B PGA Gain (Bits 5:0)

Function:

Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to

+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.

Table 7. MCLK Frequency

MCLK Divider

MCLK Freq2

MCLK Freq1

MCLK Freq0

÷1

000

÷1.5

001

÷2

010

÷3

011

÷4

100

Reserved

101

Reserved

76543

210

Reserved

PGAOut

Reserved

Table 8. PGAOut Source Selection

PGAOut

PGAOutA & PGAOutB

High Impedance

PGA Output

76543

210

Reserved

Gain5

Gain4

Gain3

Gain2

Gain1

Gain0

76543

210

Reserved

Gain5

Gain4

Gain3

Gain2

Gain1

Gain0

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