CDCLVD110

PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

SCAS684 – SEPTEMBER 2002

5

POST OFFICE BOX 655303

control register characteristics over recommended operating free-air temperature range,

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fMAX

Maximum frequency of shift register

100

150

MHz

tsu

Setup time, clock to SI

2

ns

th

Hold time, clock to SI

1.5

ns

tremoval

Removal time, enable to clock

1.5

ns

tw

Clock pulse width, minimum

3

ns

VIH

Logic input high

VDD = 2.5 V

2

V

VIL

Logic input low

VDD = 2.5 V

0.8

V

I

Input current, CK pin

VV

–5

5

A

IIH

Input current, SI and EN pins

VI = VDD

10

30

µA

I

Input current, CK pin

V

GND

–10

–30

A

IIL

Input current, SI and EN pins

VI = GND

–5

5

µA

specification of control register

The CDCLVD110 is provided with an 11-bit, serial-in shift register and an 11-bit control register. The control

Register enables/disables each output clock and selects either CLK0 or CLK1 as the input clock. The

CDCLVD110 has two modes of operation:

Programmable Mode (EN=1)

The shift register utilizes a serial input (SI) and a clock input (CK). Once the shift register is loaded with 11

output pair, and the tenth bit (bit 9) enables the Q0, Q0 pair. The eleventh bit (bit 10) on SI selects either

CLK0 or CLK1 as the input clock; a bit value of 0 selects CLK0, whereas a bit value of 1 selects CLK1. To

restart the control register configuration, a reset of the state machine must be done with a clock pulse on CK

(shift register clock input) and EN set to low. The control register can be configured only once after each

reset.

Standard Mode (EN=0)

In this mode, the CDCLVD110 is not programmable and all the clock outputs are enabled. The clock input

(CLK0 or CLK1) is selected with the SI pin, as is shown in the table entitled control register.

state-machine inputs

EN

SI

CK

OUTPUT

L

L

X

All outputs enabled, CLK0 selected, control register disabled, default state

L

H

X

All outputs enabled, CLK1 selected, control register disabled

H

L

↑

First stage stores L, other stage stores data of previous stage

H

H

First stage stores H, other stage stores data of previous stage

L

X

Reset of state machine, shift and control registers

control register

BIT 10

BITS [0–9]

QN[0–9]

L

H

CLK0

H

H

CLK1

X

L

Outputs disabled