CDCLVD110

PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

SCAS684 – SEPTEMBER 2002

1

POST OFFICE BOX 655303

Clock-Distribution applications

10 LVDS Differential Clock Outputs

1.1 GHz

Enables Disables Outputs, Selectable

CLK0, CLK0 or CLK1, CLK1 Inputs

Range

Down)

description

The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10

pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is

specifically designed for driving 50-

Ω transmission lines.

When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can

be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the

shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the

outputs are not programmable and all outputs are enabled.

The CDCLVD110 is characterized for operation from –40

°C to 85°C.

Copyright

 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TQFP PACKAGE

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