CDCLVD110

PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

SCAS684 – SEPTEMBER 2002

6

POST OFFICE BOX 655303

serial input (SI) sequence

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CLK_SEL

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

truth table for control logic

CK

EN

SI

CLK0

CLK0

CLK1

CLK1

Q (0–9)

Q(0–9)

L

L

L

L

H

X

X

L

H

L

L

L

H

L

X

X

H

L

L

L

L

Open

Open

X

X

L

H

L

L

H

X

X

L

H

L

H

L

L

H

X

X

H

L

H

L

L

L

H

X

X

Open

Open

L

H

All outputs enabled

X = Don’t care

APPLICATION INFORMATION

Fail-Safe information:

fail-safe biasing at input pins can be accomplished with a 10-k

Ω pullup resistor from CLK0/CLK1 to VDD and

a 10-k

Ω pulldown resistor from CLK0/CLK1 to GND.

LVDS Receiver Input termination:

The LVDS receiver inputs need to have 100-

Ω termination resistors placed as close as possible across the input

pins.

Control Inputs termination:

No external termination is required. The CK control input has an internal 120-k

Ω pullup resistor while SI– and

EN– control inputs each have an internal 120-k

Ω pulldown resistor. If the control pins are left open per the

default, all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled.