Rev 1.2

Page 4 of 10

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Block Diagram

Device Operating Modes and Outputs

The SiT8021 supports a ≤0.7 µA standby mode for battery-

powered and other power sensitive applications. The

switching between the active and standby modes is

controlled by the logic level on the ST pin as shown in the

table below.

Table 4. Operating Modes and Output States

ST Pin

MODE

OUTPUT

IDD Example

LOW

Active

Specified

frequency

60 µA @ 3.072 MHz

FLOAT

Active

with 200 k

Ω

internal pull-down

Specified

frequency

60 µA @ 3.072 MHz

HIGH

Standby

Hi-Z,

pulled-down with

1 M

Ω impedence

1.3 µA

Active Mode

The SiT8021 operates in the active mode when the ST pin

is at logic LOW or FLOAT. In the active mode, the device

uses the on-chip frequency synthesizer to generate an

output from the internal MEMS resonator reference. The

frequency of the output is factory programmed based on

the device ordering code.

Standby Mode

The SiT8021 operates in the standby mode when the ST

pin is at logic HIGH. In the standby mode, all internal

circuits with the exception of the MEMS oscillator circuit

and the ST pin detection logic are turned off to reduce

power consumption. While in standby mode, the input

impedance of the ST pin is increased to further reduce

system-level power consumption.

The output driver of the device in the standby mode is

pulled-down

with 1 MΩ impedance.

Output During Startup and Resume

The SiT8021 starts up with the output disabled. The output is

enabled once all internal circuit blocks are active, and logic

LOW or FLOAT is detected on the ST pin.

As shown in Table 4, logic HIGH at the ST pin forces the

SiT8021 into the “standby” state, causing the output to disable.

Upon pulling the ST pin LOW, the device enters the “resume”

state, keeping the output disabled. Once the “resume” state

ends, the device output enables.

The first clock pulse after startup or resume is accurate to the

rated stability.

Low Power Design Guidelines

For high EM noise environments, we recommend the following

design guidelines:



Place oscillator as far away from EM noise sources as

possible (e.g., high-voltage switching regulators, motor

drive control).



Route noisy PCB traces, such as digital data lines or high

di/dt power supply lines, away from the SiTime oscillator.



Place a solid GND plane underneath the SiTime oscillator

to shield the oscillator from noisy traces on the other

board layers.

Manufacturing Guidelines



No Ultrasonic or Megasonic Cleaning: Do not subject the

SiT8021

to

an

ultrasonic

or

megasonic

cleaning

environment. Permanent damage or long-term reliability

issues to the device may occur in such an event.



Applying board-level underfill (BLUF) to the device is

acceptable, but will cause a slight shift of few ppm in the

initial frequency tolerance. Tested with UF3810, UF3808,

and FP4530 underfill.



Reflow profile, per JESD22-A113D.



For additional manufacturing guidelines and marking/

tape-reel instructions, click on the following link:

sitime.com/component/docman/doc_download/243-

manufactuing-notes-for-sitime-oscillators

Figure 2. SiT8021 Block Diagram