Rev 1.2

Page 5 of 10

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Test Circuit and Waveform

0.01µF

Power

Supply

ST

Test

Point

15pF

(including probe

and fixture

capacitance)

VDD

OUT

GND

Figure 3. Test Circuit

80% Vdd

High Pulse

(TH)

50%

20% Vdd

Period

tf

tr

Low Pulse

(TL)

Figure 4. Waveform[4]

Note:

4.

Duty Cycle is computed as Duty Cycle = TH/Period.

Timing Diagram

Min. Operating Voltage

Vdd

VDD - Pin 4 Voltage

CLK Output

T_start

T_start: Time to valid clock output from power on

NO Glitch first cycle

Figure 5. Startup Timing[5, 6]

50% Vdd

Vdd

ST - Pin 1 Voltage

CLK Output

T_resume

T_resume: Time to valid clock output from the

time ST pin crosses 50% threshold

Figure 6. Resume Timing[5, 6]

50% Vdd

Vdd

ST – Pin 1 Voltage

CLK Output

T_Stdby: Time for output to go high-Z from the time

ST pin crosses 50% threshold

HiZ

T_Stdby

Figure 7. Standby Timing[5]

Notes:

5.

SiT8021 supports “no runt” pulses and “no glitch” output during startup or resume.

6.

SiT8021 supports gated output which is accurate within rated frequency stability from the first cycle.