FL663 datasheet(13/15 Pages) ONSEMI

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FL663

• Rev. 1.0

VDD Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally at

16 V and 7.5 V, respectively. During startup, the VDD

capacitor (CVDD) must be charged to 16 V. The VDD

capacitor (CVDD) continues to supply VDD until power can

be delivered from the auxiliary winding of the main

transformer. VDD is not allowed to drop below 7.5 V

during this startup process. This UVLO hysteresis

window ensures that VDD capacitor (CVDD) properly

supplies VDD during startup.

VDD Over-Voltage Protection (OVP)

The

OVP

prevents

damage

from

over-voltage

conditions. If the VDD voltage exceeds 28 V at open-loop

feedback condition, the OVP is triggered and the PWM

switching is disabled. The OVP has a debounce time

(typically 200 µs) to prevent false triggering due to

switching noises.

Thermal Shutdown Protection (TSD)

The built-in temperature-sensing circuit shuts down

PWM output if the junction temperature exceeds 140°C.

There is a hysteresis of 15°C.

Pulse-by-Pulse Current Limit

When the current sensing voltage (VCS) across the

current-sense

resistor

(RSense)

MOSFET

(Q1)

exceeds the internal threshold of 0.8 V, the MOSFET

(Q1) is turned off for the remainder of switching cycle. In

normal operation, the pulse-by-pulse current limit is not

triggered because the peak current is limited by the

control loop.

Leading-Edge Blanking (LEB)

Each time the power MOSFET (Q1) switches on, a turn-

on spike occurs at the sense resistor (RSense). To avoid

premature termination of the switching pulse, a leading-

edge blanking time is built in. Conventional RC filtering

can be omitted. During this blanking period, the current-

limit comparator is disabled and cannot switch off the

gate driver.

Gate Output

The FL663 output stage is a fast totem-pole gate driver.

Cross conduction has been avoided to minimize heat

dissipation, increase efficiency, and enhance reliability.

The output driver is clamped by an internal 15 V Zener

diode to protect power MOSFET transistors against

undesired over-voltage gate signals.

Built-in Slope Compensation

The sensed voltage across the current-sense resistor is

used for Current Mode control and pulse-by-pulse

current limiting. Built-in slope compensation improves

stability and prevents sub-harmonic oscillations due to

peak-current

mode

control.

The

FL663

has

synchronized, positive-slope ramp built-in at each

switching cycle.

Noise Immunity

Noise from the current sense or the control signal can

cause

significant

pulse-width

jitter,

particularly

Continuous-Conduction

Mode.

While

slope

compensation helps alleviate these problems, further

precautions should still be taken. Good placement and

layout practices should be followed. Avoiding long PCB

traces and component leads, locating compensation

and filter components near the FL663, and increasing

the power MOSFET gate resistance are advised.

Operation Area

Figure 23 shows operation area. FL663 has two

switching frequency (fS) in Constant Current Mode. One

is 50 kHz. In this case, FL663 can be operated with best

condition for LED illumination. The output voltage range

is between normal output voltage (VO

N) and 50% of

normal output voltage (VO

N). The other is 33 kHz. When

the output voltage is dropped by decreasing the number

of LEDs, the output voltage (VO) drops under 50% of

normal voltage (VO

N). At that time, V

DD drops to near

UVLO protection and triggers protection. To avoid

33 kHz, VO

N should be designed with enough margin.

fS = 50kHz

fS = 33kHz

0.5*VO

Constant Voltage

Operation

Constant Current

Operation

Protection

UVLO

Figure 23.

Operation Area

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