MP8843 – 6V, 3A, SYNCHRONOUS, STEP-DOWN SWITCHER WITH I

MP8843 Rev. 1.0

www.MonolithicPower.com

6

7/15/2016

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© 2016 MPS. All Rights Reserved.

I

Parameter

Symbol

Condition

Cb = 100pF

Cb = 400pF

Units

Min

Max

Min

Max

SCLH and SCL clock

frequency

0

3.4

0

0.4

MHz

Set-up time for repeated

start condition

160

-

600

-

ns

Hold time for repeated start

condition

160

-

600

-

ns

SCL clock low period

160

-

1300

-

ns

SCL clock high period

60

-

600

-

ns

Data set-up time

10

-

100

-

ns

Data hold time

0

70

0

-

ns

SCLH signal rise time

10

40

20

300

ns

SCLH signal rise time after a

repeated start condition and

an acknowledge bit

10

80

20

300

ns

SCLH signal fall time

10

40

20

300

ns

SDAH signal rise time

10

80

20

300

ns

SDAH signal fall time

10

80

20

300

ns

Stop condition set-up time

160

-

600

-

ns

Bus free time between stop

and start condition

160

-

1300

-

ns

Data valid time

-

16

-

90

ns

Data valid acknowledge time

-

160

-

900

ns

Bus line capacitive load

SDAH and SCLH line

-

100

-

400

pF

SDAH + SDA line

and SCLH + SCL line

-

400

-

400

pF

Low-level noise margin

For each connected

device

-

-

V

High-level noise margin

For each connected

device

-

-

V

NOTE:

Vcc is the I