MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER

MP8868 Rev.1.1

www.MonolithicPower.com

18

5/15/2015

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consisting of a data line (SDA) and a clock line

(SCL). The lines are externally pulled to a bus

voltage when they are “idle”. Connecting to the

line, a master device generates the SCL signal

and

device

address

and

arranges

the

communication sequence. MP8868 interface is

the power supply solution. The output voltage,

transition

slew

rate

or

other

interesting

parameters can be instantaneously controlled

MP8868 is “62” (HEX) or “1100010” (BINARY)

and is “6A” (HEX) or “1101010” if pull A0 pin to

ground.

Data validity

One clock pulse is generated for each data bit

transferred. The data on the SDA line must be

stable during the HIGH period of the clock. The

HIGH or LOW state of the data line can only

change when the clock signal on the SCL line is

LOW (see Figure.6).

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Figure 6: Bit transfer on the I

The START and STOP are signaled by the

master device which signifies the beginning and

condition is defined as the SDA signal

transitioning from HIGH to LOW while the SCL

is HIGH. The STOP condition is defined as the

SDA signal transitioning from LOW to HIGH

while the SCL is HIGH as shown in Figure 7.

SDA

SCL

P

STOP condition

SDA

SCL

S

START condition

Figure 7: START and STOP Conditions

START and STOP conditions are always

generated by the master. The bus is considered

to be busy after the START condition. The bus

is considered to be free again after a minimum

of 4.7uS after the STOP condition. The bus

stays busy if a repeated START (Sr) is

generated instead of a STOP condition. The

START

(S)

and

repeated

START

(Sr)

conditions are functionally identical.

Transfer Data

Every byte put on the SDA line must be 8-bits

long. Each byte has to be followed by an

acknowledge bit. The acknowledge-related

clock pulse is generated by the master. The

transmitter releases the SDA line (HIGH) during

the acknowledge clock pulse. The receiver

must pull down the SDA line during the

acknowledge clock pulse so that it remains

stable LOW during the HIGH period of this

clock pulse.

Data transfers follow the format shown in Figure

8. After the START condition (S), a slave

address is sent. This address is 7 bits long

followed by an eighth bit which is a data

direction bit (R/W) - a ‘zero’ indicates a

transmission (WRITE), a ‘one’ indicates a

request for data (READ). A data transfer is

always terminated by a STOP condition (P)

generated by the master. However, if a master

still wishes to communicate on the bus, it can

generate a repeated START condition (Sr) and

address another slave without first generating a

STOP condition.

S

1 7

8

9

1 7

8

9

1 7

8

9

P

STOP

condition

START

condition

DATA

ACK

DATA

ACK

ADDRESS

ACK

R/W

SDA

SCL

Figure 8: A complete data transfer

The MP8868 requires a start condition, a valid

byte for a single data update. After receipt of

each byte, MP8868 acknowledges by pulling

the SDA line low during the high period of a

the MP8868. MP8868 performs an update on

the falling edge of the LSB byte.