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MP8869SGL Datasheet(PDF) 34 Page - Monolithic Power Systems

Part # MP8869SGL
Description  18V, 12A, High-Efficiency, Wide-Input, Synchronous, Step-Down Converter with Integrated Telemetry via I2C Interface
PDF  39 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8869SGL Datasheet(HTML) 34 Page - Monolithic Power Systems

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MP8869S
– 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
MP8869S Rev. 1.03
www.MonolithicPower.com
34
1/18/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
External Bootstrap Diode
An external bootstrap diode can enhance the
efficiency of the regulator given the following
conditions:
 VOUT is 5V or 3.3V
 Duty cycle is high: D > 50%
In these cases, add an external BST diode from
VCC to BST (see Figure 13).
MP8869S
Figure 13: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
IN4148, and the recommended BST capacitor
value is 0.1µF to 1µF.
Connect VCC to VIN at a Low Input Voltage
VCC can be connected to VIN directly when
VIN is lower than 3.5V. This helps improve the
MP8869S
’s
low
input
voltage
efficiency
performance. To use this application set-up, the
VIN spike voltage must be limited below 4V,
otherwise VCC may be damaged.
PCB Layout Guidelines (9)
Efficient
PCB
layout
is
critical for
stable
operation.
A
four-layer
layout
is
strongly
recommended
to
achieve
better
thermal
performance. For best results, refer to Figure
14 and follow the guidelines below.
1. Place the high-current paths (PGND, VIN,
and SW) very close to the device with short,
direct, and wide traces.
2. Keep the VIN and PGND pads connected
with large copper planes.
3. Use at least two layers for the VIN and
PGND trace to achieve better thermal
performance.
4. Add several vias close to the VIN and
PGND pads to help with thermal dissipation.
5. Place the input capacitors as close to VIN
and PGND as possible.
6. Place the decoupling capacitor as close to
VCC and PGND as possible.
7. Place the external feedback resistors next
to FB.
8. Ensure that there is no via on the FB trace.
9. Keep the switching node SW short and
away from the feedback network.
10. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
NOTE:
9)
The
recommended
layout
is
based
on
the
Typical
Application circuit on page 36 to page 38.



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