MP3427 – 17A, 600kHz, 8V WIDE INPUT RANGE SYNCHRONOUS BOOST CONVERTER IN A SMALL 3X4MM QFN PACKAGE

MP3427 Rev. 1.0

www.MonolithicPower.com

16

12/26/2014

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The MOSFET voltage rating should be equal to

or greater than the output voltage. The average

current rating must be greater than the maximum

load current. The peak-current rating must be

greater than the peak-inductor current. If a

Schottky diode is used as the output rectifier, the

same specifications should be considered.

Compensation

The output of the transconductance error

amplifier (COMP) is used to compensate the

regulation control system. The system uses two

poles and one zero to stabilize the control loop.

compensation

capacitor

and

the

compensation

resistor

These

are

determined by the equations:

P1

LOAD

OUT

1

F(Hz)

2R

C

=

×π×

×

Z1

COMP

COMP

1

F(Hz)

2R

C

=

×π×

×

The DC loop gain is:

)

/

(

2

2

V

V

V

R

G

V

R

V

A

A

OUT

COMP

CS

FB

LOAD

IN

VEA

VDC

×

×

×

×

×

×

=

regulation threshold.

exists in continuous conduction mode (CCM); the

inductor current does not drop to zero each cycle.

The frequency of the right-half-plane zero is:

2

LOAD

IN

RHP

OUT

R

V

F(

) (Hz)

2L

V

=×

×π×

The right-half-plane zero increases the gain and

reduces the phase simultaneously, resulting in a

smaller phase and gain margin. The worst case

happens during conditions of minimum input

voltage and maximum output power.

Compensation recommendations are listed in the

“Typical Application Circuits” section.

PCB Layout Guide

High-frequency switching regulators require very

careful layout for stable operation and low noise.

All components must be placed as close to the IC

as possible.

1

2

3

4

5

6

7

8

1

2

2

1

1

2

1

2

2

1

2

1

1

2

1

2

Figure 4. PCB Layout Reference

Refer to Figure 4 and the recommended layout

guidelines below to optimize performance:

1. Make the output loop consisting of SW,

PGND, Q1 and C2 as small as possible.

2. Place FB divider R1 and R2 as close as

possible to FB.

3. Route the sensing traces (SENSE and IN) in

parallel closely with a small closed area. The

0805 package is recommended for the

sensing resistor R4 in order to reduce

parasitic inductance.

4. Connect FB and OUT feedback from the

output capacitor C2.

5. Connect the compensation components and

SS capacitor to AGND with a short loop.

6. Make a short connection from the VDD

capacitor to AGND. Do NOT connect to

PGND net before connecting to IC-AGND.

7. The input path consisting of C1, L1, SW,

PGND, BST path, and SDR path should be

as short as possible.