MP8765 ─ 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

MP8765 Rev. 1.01

www.MonolithicPower.com

18

2/10/2015

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simplification,

the

output

ripple

can

be

approximated as:

OUT

OUT

OUT

ESR

SW

IN

VV

V(1

) R

FL

V

Δ=

× −

×

×

(24)

Maximum output capacitor limitation should be

also considered in design application. MP8765

has an around 7ms soft-start time period. If the

output capacitor value is too high, the output

voltage can’t reach the design value during the

soft-start time, and then it will fail to regulate. The

limited approximately by:

O _ MAX

LIM _ AVG

OUT

ss

OUT

C(I

I

) T / V

=−

×

(25)

Inductor

The inductor is necessary to supply constant

current to the output load while being driven by

the switched input voltage. A larger-value

inductor will result in less ripple current that will

result in lower output ripple voltage. However, a

larger-value inductor will have a larger physical

footprint, higher series resistance, and/or lower

saturation current. A good rule for determining

the inductance value is to design the peak-to-

peak ripple current in the inductor to be in the

range of 30% to 40% of the maximum output

current, and that the peak inductor current is

below the maximum switch current limit. The

inductance value can be calculated by:

OUT

OUT

SW

L

IN

VV

L(1

)

FI

V

=× −

×Δ

(26)

current.

The inductor should not saturate under the

maximum inductor peak current, where the peak

inductor current can be calculated by:

OUT

OUT

LP

OUT

SW

IN

VV

II

(1

)

2F

L

V

=+

× −

×

(27)

PCB Layout Guide

1. The high current paths (GND, IN, and SW)

should be placed very close to the device

with short, direct and wide traces.

2. Put the input capacitors as close to the IN

and GND pins as possible.

3. Put the decoupling capacitor as close to the

VCC and GND pins as possible. Place the

Cap close to AGND if the distance is long.

And place >3 Vias if via is required to reduce

the leakage inductance.

4. Keep the switching node SW short and away

from the feedback network.

5. The external feedback resistors should be

placed next to the FB pin. Make sure that

there is no via on the FB trace.

6. Keep the BST voltage path (BST, C3, and

SW) as short as possible.

7. Keep the IN and GND pads connected with

large copper to achieve better thermal

performance.

Add

several

Vias

with

10mil_drill/18mil_copper_width close to the

IN and GND pads to help on thermal

dissipation.

8. Four-layer layout is strongly recommended to

achieve better thermal performance.

Note:

Please refer to the PCB Layout Application Note for more details.