HF01B00/01/02/03/04

–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR

HF01B00/01/02/03/04 Rev. 1.2

www.MonolithicPower.com

10

4/9/2013

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2013 MPS. All Rights Reserved.

Figure 5 shows the waveform of valley switching

detection on auxiliary winding and the MOSFET

Drain-Source voltage.

Valley point

45mV

Figure 5

—Valley Switching Detection

An internal minimum off-time limiter prevents the

MOSFET from turning on until the 7.8us off-time

limit is passed.. Thus the minimum off time of

primary switch will be longer than 7.8us and the

switching

frequency

would

be

lower

than

1/(Ton+7.8us). This ensures that the switching

frequency is below 150kHz, which is below the

CISPER22 EMI minimum limit. Figure 6 and 7

shows the minimum turn-off time limit of the

primary switch.

6.8us

Figure 6

—Minimum Turn-off Time Limit

8.8us

Figure 7

—Minimum Turn-off Time Limit

Over-voltage Protection (OVP)

The positive plateau of the auxiliary winding

voltage is proportional to the output voltage. The

Over Voltage Protection unit detects the auxiliary

winding voltage signal by VSD pin instead of

directly monitoring the output voltage.

Figure 8 shows the external circuit of VSD pin. If

the voltage of this pin exceeds 6V, the OVP is

triggered, and the HF01B00/01/02/03/04 stops

switching and goes into latched fault condition.

That means the regulator stays fully latched in

this position until the Vcc is decreased down to

3V, e.g. when the user unplugs the power supply

from the main supply and re-plugs it.

VSD

HF01B00-04

Auxiliary

Winding

6V

OVP

Figure 8

—OVP Circuit

The internal resistance of VSD pin is 24kΩ, so

the OVP triggered point could be programmed

formula:









S

INT

OVP

S

OVP

OVP

A

INT

A

N

6 R

R

N

6 24k R

V

N

R

N

24k











