HT6116 datasheet(5/10 Pages) HOLTEK

5 / 10 page

Timing Diagrams

Read cycle

(1)

Functional Description

The HT6116-70 is a 2K

×8 bit SRAM. When the

CS pin of the chip is set to “low”, data can be

written in or read from eight data pins; other-

wise, the chip is in the standby mode. During a

write cycle, the data pins are defined as the

input state by setting the WE pin to low. Data

should be ready before the rising edge of the WE

pin according to the timing of the writing cycle.

While in the read cycle, the WE pin is set to high

and the OE pin is set to low to define the data

pins as the output state. All data pins are de-

fined as a three-state type, controlled by the OE

pin. In both cycles (namely, write and read cy-

cles), the locations are defined by the address

pins A0~A10. The following table illustrates the

relations of WE, OE, CS and their correspond-

ing mode.

Mode

D0~D7

Standby

High–Z

Read

Dout

Read

High–Z

Write

Din

where

X stands for “don’t care”.

H stands for high level

L stands for low level.

HT6116-70

3rd July ’97

HT6116 Datasheet(PDF) 5 Page - Holtek Semiconductor Inc