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dc1826afa

DEMO MANUAL DC1826A

AC-Coupling the Inputs

The circuit in Figure 5 can be AC-coupled on the DC1826A

by putting JP1 and JP2 in the AC position and adding a

1k resistor at the R11 and R40 locations. Using just JP1

and adding R11 allows a single-ended input signal to be

AC-coupled. AC-coupling the inputs may degrade the

distortion performance of the ADC due to nonlinearity of

the coupling capacitors (C12 and C31).

Data Collection

For SINAD, THD or SNR testing, a low noise, low distortion

generator such as the B&K Type 1051 or Stanford Research

DS360 should be used. A low jitter RF oscillator such as

the HP8644 or DC1216A-A is used as the clock source.

This demo board is tested in-house by attempting to du-

plicate the FFT plot shown in Figure 7a of the LTC2389-18

data sheet. This involves using a 2.5MHz clock source,

along with a sinusoidal generator at a frequency of 2kHz.

The input signal level is approximately –1dBfs. The input

is level shifted and filtered with the circuit shown in Fig-

ure 6. A typical FFT obtained with DC1826A is shown in

Figure 7. Note that to calculate the real SNR, the signal

level (F1 amplitude = –0.998dB) has to be added back to

the SNR that PScope displays. With the example shown in

Figure 7 this means that the actual SNR would be 98.50dB

instead of the 97.52dB that PScope displays. Taking the

RMS sum of the recalculated SNR and the THD yields a

SINAD of 98dB which is fairly close to the typical number

for this ADC.

There are a number of scenarios that can produce mis-

leading results when evaluating an ADC. One that is

common is feeding the converter with a frequency that

is a submultiple of the sample rate, and which will only

exercise a small subset of the possible output codes.

The proper method is to pick an M/N frequency for the

input sine wave frequency. N is the number of samples

in the FFT. M is a prime number between one and N/2.

Multiply M/N by the sample rate to obtain the input sine

wave frequency. Another scenario that can yield poor

results is if you do not have a signal generator capable of

ppm frequency accuracy or if it cannot be locked to the

clock frequency. You can use an FFT with windowing to

reduce the “leakage” or spreading of the fundamental, to

get a close approximation of the ADC performance. If an

amplifier or clock source with poor phase noise is used,

the windowing will not improve the SNR.

Layout

As with any high performance ADC, this part is sensitive

to layout. The area immediately surrounding the ADC on

the DC1826A should be used as a guideline for placement,

and routing of the various components associated with the

ADC. Here are some things to remember when laying out

a board for the LTC2389-18. A ground plane is necessary

to obtain maximum performance.

Keep bypass capacitors as close to supply pins as pos-

sible. Use individual low impedance returns for all bypass

capacitors. Use of a symmetrical layout around the analog

inputs will minimize the effects of parasitic elements. Shield

analog input traces with ground to minimize coupling from

other traces. Keep traces as short as possible.

Component Selection

When driving a low noise, low distortion ADC such as

the LTC2389-18, component selection is important so

as to not degrade performance. Resistors should have

low values to minimize noise and distortion. Metal film

resistors are recommended to reduce distortion caused

by self heating. Because of their low voltage coefficients,

to further reduce distortion NPO or silver mica capacitors

should be used. Any buffer used to drive the LTC2389-18

should have low distortion, low noise and a fast settling

time such as the LT6350.

DC1826A SETUP

Figure 6. Level-Shift Circuit