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SC16C650B Datasheet(PDF) 29 Page - NXP Semiconductors

Part # SC16C650B
Description  5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder
PDF  51 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC16C650B Datasheet(HTML) 29 Page - NXP Semiconductors

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Philips Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
Product data
Rev. 03 — 10 December 2004
29 of 51
9397 750 14451
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C650B provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
1
MSR[1]
∆DSR [1]
Logic0=No DSR change (normal default condition).
Logic1=The DSR input to the SC16C650B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
0
MSR[0]
∆CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C650B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
Table 21:
Modem Status Register bits description…continued
Bit
Symbol
Description
Table 22:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Automatic CTS flow control.
Logic0=Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.
0 = Automatic RTS flow control is disabled (normal default condition).
1 = Enable Automatic RTS flow control.



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