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LTC3331 Datasheet(PDF) 13 Page - Linear Technology

Part # LTC3331
Description  Nanopower Buck-Boost DC/DC with Energy Harvesting Battery Charger
PDF  34 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3331 Datasheet(HTML) 13 Page - Linear Technology

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LTC3331
13
3331fc
For more information www.linear.com/LTC3331
Supercapacitor Balancer
Quiescent Current vs VSCAP
Supercapacitor Balancer
Source/Sink Current
Battery Connect Transient
Battery Connect/Disconnect
vs Temperature
Battery Connect/Disconnect
vs Temperature
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
2.6
2.8
3.2
3.4
3.6
50
4.4
3331 G58
3.0
0
–25
75
100
25
125
3.8
4.0
4.2
CONNECT, BAT_OUT
CONNECT, BAT_IN
DISCONNECT, BAT_OUT, BAT_IN
4.0, 4.1, 4.2 FLOAT
LBSEL = 0
IBAT_OUT = 1mA
TEMPERATURE (°C)
–50
2.6
2.8
3.2
3.4
3.6
50
4.4
3331 G59
3.0
0
–25
75
100
25
125
3.8
4.0
4.2
CONNECT, BAT_OUT
CONNECT, BAT_IN
DISCONNECT, BAT_OUT, BAT_IN
4.0, 4.1, 4.2 FLOAT
LBSEL = 1
IBAT_OUT = 1mA
500ms/DIV
3331 G60
CBAT_IN = 1mF
CBB_IN = 22µF, BB_IN TIED TO BAT_OUT
1mA LOAD AT VOUT
FLOAT[1:0] = 11, LBSEL = 0
500mV/DIV
BAT_OUT
BAT_IN
VOUT
0V
BATTERY
DISCONNECTED
VSCAP (V)
2
250
200
150
100
50
0
3
4
4.5
5
3.5
3330 G61
5.5
2.5
85°C
125°C
25°C
–40°C
VBAL/VSCAP (%)
0
50
40
30
20
10
0
–10
–20
20 30
50 60 70 80 90
40
3330 G62
100
10
SCAP = 5V
SCAP = 2.5V
PIN FUNCTIONS
BAL (Pin 1): Supercapacitor Balance Point. The common
node of a stack of two supercapacitors is connected to
BAL. A source/sink balancing current of up to 10mA is
available. Tie BAL along with SCAP to GND to disable the
balancer and its associated quiescent current.
SCAP (Pin 2): Supply and Input for Supercapacitor
Balancer. Tie the top of a 2-capacitor stack to SCAP and
the middle of the stack to BAL to activate balancing. Tie
SCAP along with BAL to GND to disable the balancer and
its associated quiescent current.
VIN2 (Pin 3): Internal Low Voltage Rail to Serve as Gate
Drive for Buck NMOS Switch. Connect a 4.7µF (or larger)
capacitor from VIN2 to GND. This pin is not intended for
use as an external system rail.
UV3, UV2, UV1, UV0 (Pins 4, 5, 6, 7): UVLO Select Bits
for the Buck Switching Regulator. Tie high to VIN2orlowto
GNDtoselectthedesiredUVLOrisingandfallingthresholds
(see Table 4). The UVLO falling threshold must be greater
than the selected VOUT regulation level. Do not float.



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