THCV219_Rev.2.30_E

Copyright©2017 THine Electronics, Inc.

THine Electronics, Inc.

Security E

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Pin Description

Pin Name

Pin #

type* Description

R9-R0

9,8,7,6,4,

3,31,30,39,38

I3

pixel data inputs

G9-G0

17,16,15,13,12,

11,33,32,41,40

I3

pixel data inputs

B9-B0

25,23,22,21,20,

18,36,34,43,42

I3

pixel data inputs

CONT1,2

37,46

I3

User defined data inputs. Active only in 32bit mode.

DE

28

I3

DE input

VSYNC

27

I3

Vsync input

HSYNC

26

I3

Hsync input

CLKIN

45

I3

Pixel clock input

TXN/P

58,57

CO

High-speed CML signal output.

LOCKN

60

I3L

Lock detect input.

Must be connected to Rx LOCKN with a 10kΩ pull-up resistor.

HTPDN

61

I3L

Hot plug detect input.

Must be connected to Rx HTPDN with a 10kΩ pull-up resistor.

PDN

47

I3L

Power down input.

H: Normal operation L: Power down

PRE

50

I3

Pre-Emphasis level select input.

H : Pre-Emphasis Enable L : Pre-Emphasis Disable

CMLDRV

64

I3

CML Outputs drive strength select input.

H : Normal drive strength L : Weak drive strength

COL**

63

I3

Data width setting.

H : 24bit L : 32bit

LFSEL**

49

I3

Frequency range setting.

H: Low frequency operation L: Normal Operation

ASYNDE

1

I3

Asynchronous DE input.

H: Normal operation (ASYNDE function disable)

L: DE input invert operation (ASYNDE function enable)

RF

2

I3

Input clock triggering edge select input for latching input data

H: Rising edge L: Falling edge

BET

62

I3

Field-BET entry.

H : Field BET Operation L : Normal Operation

TEST1

48

-

Test pin, must be “L” for normal operation.

TEST2

52

-

Test pin, must be “L” for normal operation.

CAPOUT

53

-

Decoupling capacitor pins.

This pin should be connected to external decoupling capacitors.

Recommended Capacitance is 2.2uF

CAPINP

54

-

Reference Input for PLL circuit.Must be tied CAPOUT.

CAPINA

55

-

Reference Input for Analog circuit.Must be tied CAPOUT.

VCC

5,14,19,29,

35,44

PS

Digital Power supply Pins

AVCC

51

PS

Analog Power supply Pin

GND

10,24,56,59

PS

Ground Pins

EXPGND

65

PS

Exposed Pad Ground

*type symbol

I3=3.3v CMOS input, I3L=Low Speed 3.3v CMOS input

CO=CML output, PS=Power Supply

**COL, LFSEL pin

COL pin and/or LFSEL pin level shall not be changed during operation. If ether pin level is changed during operation,

PDN shall be toggled (H-> L -> H) after the change.