THCV233-THCV234_Rev.3.10_E

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DE signal (TLC[6] / DEIN) Input Requirement

There are some requirements for DE signal as described in Figure 3, Figure 4 Figure 14 and Table 24.

If DE=Low, control data of same cycle and particular assigned data bit ‘CTL’ except the first and the last pixel are

transmitted. Otherwise video data are transmitted during DE=High.

Control data from receiver in DE=High period are previous data of DE transition. See Figure 4.

The length of DE being low and high is at least 2 clock cycles long, as described in Figure 14 and Table 24.

Data Enable must be toggled like High -> Low -> High at regular interval.

Data bit : R/G/B, CONT

Control bit : V,HSYNC

Data bit : CTL*

H

L

DE

THCV234

THCV233

R/G/B,

CONT,

CTL

V,

HSYNC

DE=H R/G/B,CONT

DE=L, CTL* except the 1st and the last pixel

other R/G/B,CONT=Low Fixed

DE=H, V,HSYNC=Fixed

DE=L, V,HSYNC

DE

*CTL are particular assigned bit among R/G/B, CONT that can carry arbitrary data during DE=Low period.

Figure 3 Conceptual diagram of the basic operation of the chipset

Figure 4 Data bit and control bit transmission when DE is from LVDS (default)

TLCLK +/-

6

5

4

3

2

1

0

D

E

V

H

3

2

1

0

TLn +/-

n=A,B,D,E

TLC +/-

6

5

4

3

2

1

0

D

E

V

H

3

2

1

0

6

5

4

3

2

1

0

D

E

V

H

3

2

1

0

6

5

4

3

2

1

0

D

E

V

H

3

2

1

0

6

5

4

3

2

1

0

D

E

V

H

3

2

1

0

6

5

4

3

2

1

0

D

E

V

H

3

2

1

0

DE=High

Active period

DE=Low

Blanking period

Data : Low fixed

H, V : Keep the last data of blanking period

THCV233

input

THCV234

output

DE input via LVDS

Data : Particular assigned bit ‘CTL’ is transmitted except the

first and the last pixel of Blanking period. / Others are Low fixed.

RLCLK +/-

6

5

4

3

2

1

0

RLn +/-

n=A,B,D,E

RLC +/-

6

5

4

3

2

1

0

6

5

4

3

2

1

0

6

5

4

3

2

1

0

6

5

4

3

2

1

0

6

5

4

3

2

1

0

Indefinite region

Indefinite region

DEOUT

(CMOS)

±3/7tTCIP

±3/7tTCIP

tRALN

tRALN

Indefinite region

Typ;5tTCIP/7

Typ;5tTCIP/7