LTM2895 datasheet(13/30 Pages) LINER

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LTM2895

2895fa

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APPLICATIONS INFORMATION

the SCK. For configured SCK2 frequencies of 50MHz and

lower, MOSI is captured on the rising edge and MISO is

shifted on the falling edge of SCK, as shown in Figure 3.

The isolated side always operates in mode (0, 0). MOSI2

sets up data on the falling edge of SCK2 and MISO2 is

captured on the rising edge of SCK2.

Third, the slave selects SS and SSB must be dedicated to

framing the operation of reading or writing data. The SS or

SSB must go low at the beginning of the SPI transaction

prior to the SCK transitions and must go high after the

last SCK rising edge transition, see Figure 4.

LOAD INPUT

LOAD input is a low jitter path available for digital to ana-

log converters that offers a low true LOAD DAC (LDAC)

input. The LOAD to LOAD2 signal is initiated on a falling

edge. The rising edge of LOAD is ignored. The rising

edge of LOAD2 is generated internally and has up to 5ns

of jitter. The low pulse width of LOAD2 is dependent on

the configured SCK2 frequency. For SCK2 frequencies of

SCK

2895 F02

MOSI

MISO

SCK

2895 F03

MOSI

MISO

SS or SSB

SCK

FRAME

2895 F04

Figure 2. SCK and Data with SCK2 Frequency

Configured for 100MHz or 66MHz

Figure 3. SCK and Data with SCK2 Frequency

Configured for 50MHz or Less

Figure 4. SPI Transaction with SS or SSB Framing SCK

40MHz or greater, LOAD2 has a pulse width of ~40ns, and

for SCK2 frequencies of 33MHz or below, LOAD2 has a

pulse width of ~60ns.

LOAD is not necessary to interact with the isolated SPI

device. When LOAD is unused connect it to VL.

READ BACK DATA

Data can be read back from the isolated side MISO2 pin

to MISO. The data read out of the MISO pin has one word

of latency data[n-1]. The MISO pin is only utilized during

transactions when the primary chip select, SS, is active.

When data is read from the isolated side's MISO2 data[n],

it is placed in a circular FIFO buffer on the logic side. The

current data in the buffer (data[n-1]) is shifted out on the

MISO output. New data from the isolated side will fill in

the buffer behind it. The very first word read out of the

buffer after a startup is all “0”s.

The LTM2895 uses read and write pointers to track the

current bit locations for data[n] and data[n-1]. If the SPI

communication is unexpectedly halted from the master

controller and then recovers or is reconnected during a

different transaction, the internal relative alignment of the

pointers may be lost resulting in an offset in the read back

data. If an offset in the data is detected, the pointers may

be resynchronized by resetting the LTM2895. To reset the

LTM2895, toggle the ON pin low for 1µs and then reload

the configuration register.

SPI PAGE MODE

SPI page mode allows large data transfers of multiple

words within a slave select frame. To operate in page

mode beyond the defined wordlength, maintain SS low

and continue clocking SCK the desired number of word-

lengthmultiples.SCKmustendonawordlengthboundary.

Further, maintain the timing between rising edges of SCK

and the timing between SS and SCK so a watchdog event

is not triggered.

The read back data on MISO is one word-length delayed.

See Figure 14 for an example of page mode operation and

the relationship of words into and out of the LTM2895.

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