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LTM2895

2895fa

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TIMING DIAGRAMS

ISOLATED INTERFACE

The isolated interface of the LTM2895 is driven by the

signal transitions on the logic side. The LOAD2 pulse

width is an internally controlled parameter based on the

configuration of SCK2. An SCK2 frequency selection of

50MHz or greater will result in a ~40ns tPWLOAD2 and a

40MHz or lower frequency will result in a ~60ns tPWLOAD2.

The falling edge of LOAD2 has low jitter and the rising

edge has ~5ns of jitter.

When connecting a SPI device to the isolated side, select

a SCK2 frequency that allows the required setup and hold

time for the device and the LTM2895. See section SCK2

FREQUENCY to select the proper operating frequency.

The isolated interface sets up data on the falling edge of

SCK2 which matches SPI mode (0, 0). MISO2 and MOSI2

timing constraints are measured against the SCK2 falling

to rising time, tSCK2L.

Figure 8. Logic Isolated Side Interface

DN-1

DN-2

DN-3

DIN

DI0

DI1

DIN-3

DIN-2

DIN-1

MOSI2

SCK2

tSCK2

SS2

tSCK2L

tSCK2H

tSCK2SS2DIS

tHMOSI2

tSUMISO2

tSS2FSCK2

MISO2

LOAD2

tPWLOAD2

2895 F08

tDLYMOSI2SCK2

tHMISO2

tDMOSI2

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