LTM4644 datasheet(8/32 Pages) LINER

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LTM4634

4634f

For more information www.linear.com/LTM4634

pin FuncTions

INTVCC (J8): Output of the Internal Bias LDO for Powering

InternalControlCircuitry.Connecta4.7µFceramiccapaci-

tor to ground for decoupling. If the voltage at CNTL_PWR

is ≤5.8V, tie the INTVCC pin to CNTL_PWR for optimum

efficiency. If the voltage at CNTL_PWR is >5.8V, leave

INTVCC floating. See the Applications Information section.

SGND (K6-K7, L6-L7): Signal Ground Connections. The

signal ground connection in the module is separated from

normal power ground (GND) by an internal 2.2Ω resistor.

This allows the designer to connect the signal ground pin

close to GND near the external output capacitors on the

regulatorchannel’soutputs.Theentireinternalsmall-signal

feedback circuitry is referenced to SGND, thus allowing

for better output regulation. See the recommended layout

in the Applications Information section.

EXTVCC (L3): External Bias Power Input. The internal bias

LDO is bypassed whenever the voltage at EXTVCC is above

4.7V. Never exceed 6V at this pin and ensure CNTL_PWR >

EXTVCC at all times to avoid reverse polarity on the internal

bias LDO. Connect a 1µF capacitor to ground when used

otherwise leave floating. Use a 5V bias or 5V output to

power this pin to improve efficiency.

FREQ/PLLLPF(L8):FrequencySetandPLLLowpassFilter

Pin. This pin is driven with a DC voltage to set the oper-

ating frequency. The recommended operating frequency

will be supplied in the efficiency graphs for optimal per-

formance. A specific frequency can be chosen as long as

the minimum on-time is not violated, and inductor ripple

current is optimized. When an external clock is used, then

the FREQ/PLLLPF pin must not be connected to any DC

voltage. The pin must be floating and will have the proper

internal compensation for the internal loop filter. See the

Applications Information section.

MODE/PLLIN(L9):ForcedContinuousMode,BurstMode,

or Pulse-Skipping Mode Selection Pin and External Syn-

chronization Input to Phase Detector Pin. Connect this pin

to SGND to force all channels into the continuous mode

of operation. Connect to INTVCC to enable pulse-skipping

mode of operation. Leave floating to enable Burst Mode

operation. A clock on the pin will force the controller into

continuousmodeofoperationandsynchronizetheinternal

oscillator. See the Applications Information section.

RUN1,RUN2,RUN3(L10,L11,K11):RunControlInputs.

A voltage above 1.3V on any RUN pin turns on that par-

ticular channel. However, forcing any of these RUN pins

below 1.15V causes that channel to shut down. Each of

the RUN pins has an internal 10k resistor to ground. This

resistor can be used with an external pull-up resistor to

the input voltage to set a UVLO for that channel, or simply

to turn on the channel. The RUN pins have a maximum

voltage of 6V. See the Applications Information section.

PGOOD12, PGOOD3 (M2, M3): Output Voltage Power

Good Indicator for VOUT1 and VOUT2 Combined, and VOUT3

Separate. The open-drain logic output is pulled to ground

when the output voltage is not within ±7.5% of the regula-

tion point.

COMP1, COMP2, COMP3 (M4, L4, K4): Current Control

Threshold and Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. The LTM4634 regulator channels are all internally

compensated for proper stability. COMP1 and COMP2 can

be tied together for PolyPhase 10A parallel operation. See

the Applications Information section.

VFB1, VFB2, VFB3 (M5, L5, K5): The Negative Input of the

Error Amplifier for Each of the Three Channels. Internally,

each of these pins is connected to their respective output

with a 60.4k precision resistor. Different output voltages

can be programmed with an additional resistor between

eachindividualVFBpinandground.InPolyPhaseoperation,

tying the VFB1 and VFB2 pins together allows for parallel

operation up to 10A. See the Applications Information

section for details.

TK/SS1,TK/SS2,TK/SS3(M9,M10,M11):OutputVoltage

TrackingandSoft-StartInputs.Whenoneparticularchannel

is configured to be the master, a capacitor to ground at

this pin sets the ramp rate for the master channel’s output

voltage. When the channel is configured to be the slave,

the VFB voltage of the master channel is reproduced by a

resistor divider and applied to this pin. Internal soft-start

currents of 1.5μA are charging the soft-start capacitors.

In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to

be shorted externally.

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