LTM4644 datasheet(14/32 Pages) LINER

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LTM4634

4634f

For more information www.linear.com/LTM4634

applicaTions inForMaTion

Low duty cycle applications may approach this minimum

on-time limit and care should be taken to ensure that:

VOUT

VIN •FREQ

> tON(MIN)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles.Theoutputvoltagewillcontinuetoberegulated,but

the output ripple and inductor ripple current will increase.

The minimum on-time can be increased by lowering the

switching frequency. A good rule of thumb is to use a

100ns on-time.

Output Voltage Tracking

Output voltage tracking can be programmed externally

using the TK/SS pins. The output can be tracked up and

downwithanotherregulator.Themasterregulator’soutput

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider to imple-

ment coincident tracking. The LTM4634 uses an accurate

60.4k resistor internally for the top feedback resistor for

each channel. Figure 3 shows an example of coincident

tracking for VOUT1 and VOUT2. VOUT1 is the master and

VOUT2 is the slave:

VSLAVE = 1+

60.4k

RTA









VTRACK

VTRACK is the track ramp applied to the slave’s track pin.

VTRACK has a control range of 0V to 0.8V, or the internal

reference voltage. When the master’s output is divided

down with the same resistor values used to set the slave’s

output, then the slave will coincident track with the master

until it reaches its final value. The master will continue to

its final value from the slave’s regulation point. Voltage

tracking is disabled when VTRACK is more than 0.8V. RTA in

Figure 3 will be equal to the RFB2 for coincident tracking.

The TK/SS pin of the master can be controlled by a capaci-

tor placed on the master regulator TK/SS pin to ground. A

1.5µA current source will charge the TK/SS pin up to the

RFB3

19.1k

RFB2

121k

RFB1

69.8k

COUT8

100µF

COUT2

220µF

47pF

1.5V

VFB1

VFB2

1.2V

3.3V

COUT5

220µF

220pF

VFB3

47pF

COUT1

220µF

CSS3

0.1µF

VOUT3

RTA

121k

SOFT-START MASTER

RAMP SET BY CSS3 OR

EXTERNAL RAMP

UVLO SET AT 4.7V ON RUN PINS.

RUN PINS CAN BE SEQUENCED OR

ENABLED FROM LOGIC CONTROL

COUT, SEE TABLE 5

RTB 60.4k

60.4k

69.8k

7.87k

CIN1

22µF

16V

CIN2

22µF

16V

CIN3

22µF

16V

CIN4

22µF

16V

COUT4

220µF

COUT7

100µF

10k

CNTL_PWR

MODE/PLLIN

RUN1

RUN2

RUN3

TK/SS2

TK/SS3

FREQ/PLLLPF

COMP1

COMP2

COMP3

PGOOD12

PGOOD3

TEMP1

TEMP2

VOUT1 VFB1

VOUT2 VFB2

VOUT3 VFB3

4633 F03

GND SGND

VIN1 SW1

VIN2

5.5V TO 16V

SW2

VIN3

LTM4634

SW3

4.7µF

6.3V

INTVCC EXTVCC

TK/SS1

VFB2

VFB3

MASTER

Figure 3. Triple Outputs (1.5V and 1.2V) with Tracking and 3.3V

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