LTM4644 datasheet(25/32 Pages) LINER

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LTM4639

4639f

For more information www.linear.com/LTM4639

Safety Considerations

TheLTM4639 doesnotprovide galvanic isolationfromVIN

to VOUT. There is no internal fuse. If required, a slow blow

fuse with a rating twice the maximum input current needs

tobeprovidedtoprotecteachunitfromcatastrophicfailure.

The fuse or circuit breaker should be selected to limit the

current to the regulator during overvoltage in case of an

internal top MOSFET fault. If the internal top MOSFET

fails, then turning it off will not resolve the overvoltage,

thus the internal bottom MOSFET will turn on indefinitely

trying to protect the load. Under this fault condition, the

input voltage will source very large currents to ground

throughthefailedinternaltopMOSFETandenabledinternal

bottom MOSFET. This can cause excessive heat and board

damage depending on how much power the input voltage

can deliver to this system. A fuse or circuit breaker can be

used as a secondary fault protector in this situation. The

LTM4639doessupportovervoltageprotection,overcurrent

protection and overtemperature protection.

Layout Checklist/Example

The high integration of the LTM4639 makes the PCB

board layout very simple and easy. However, to optimize

its electrical and thermal performance, some layout

considerations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output

capacitors next to the VIN, GND and VOUT pins to

minimize high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• Tominimizetheviaconduction loss andreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put vias directly on the pad, unless they are

capped or plated over.

• Place test points on signal pins for testing.

• Use a separated SGND ground copper area for

components connected to signal pins. Connect the

SGND to GND underneath the unit.

• For parallel modules, tie the COMP and VFB pins

together. Use an internal layer to closely connect these

pins together.

Figure21givesagoodexampleoftherecommendedlayout.

APPLICATIONS INFORMATION

Figure 21. Recommended PCB Layout

PGND

VIN

4639 F21

CONTROL

SIGNAL

GROUND

VOUT

COUT

CIN

COMPA

TEMP+

TEMP–

CPWR

OT_TEST

COMPB

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