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LTC2000A

2000afb

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OPERATION

Table 6. Clock Synchronizer SPI Registers

ADDRESS BIT

NAME

DESCRIPTION

0x05

[1:0]

SYNC_PS

Synchronizer Phase Select. Selects phase of internal data multiplexer. SYNC_PS is read-only when SYNC_MSYN = 0.

SYNC_MSYN Synchronizer Manual Mode Select. When SYNC_MSYN = 0, SYNC_PS is set automatically by the clock synchronizer

based upon SYNC_PH. When SYNC_MSYN = 1, SYNC_PS must be set by the user.

0x06

[7:0]

SYNC_PH

Synchronizer Phase Comparator Outputs. SYNC_PH indicates the phase of the LVDS data clock (DCKIP/N) relative to

the DAC sample clock (CKP/N) divider used to control the data multiplexer. SYNC_PH is read only.

SYNC_PH

OPTIMAL SYNC_PS SETTING

DUAL-PORT MODE

SINGLE-PORT MODE

0x03

0x04

0x05

0x15

0x25

0x35

0x45

0x55

0x54

0x53

0x52

0x51

0x50

0x40

0x30

0x20

0x10

0x00

0x01

0x02

Note: Registers 0x05 and 0x06 reset to 0x00 (default).

phase of the MUX control signals as needed to track any

slow drift in the phase between the DCKIP/N and CKP/N

due to supply and temperature variation. This ensures that

data is sampled correctly by CKP/N.

Use SPI registers 0x05 and 0x06 (Table 6) to observe and

control the operation of the synchronizer. Upon power-up,

apply clocks to CKP/N and DCKIP/N and set DCKI_EN = 1

(register 0x03) to enable the LVDS data clock receiver.

Allow at least 1ms after the clocks have stabilized for the

synchronizer to initialize, after which the LTC2000A is

ready to accept LVDS input data.

The synchronizer uses phase comparators to monitor

the phase of the data input clock relative to the sample

clock divider which controls the MUX. The outputs of

these phase comparators (SYNC_PH) may be observed

in register 0x06.

TheSYNC_PSbitscontrolthephaseofthedatamultiplexer.

For SYNC_MSYN = 0, the SYNC_PS bits are read-only and

are automatically adjusted by the synchronizer as needed,

based upon the phase of DCKIP/N indicated by SYNC_PH.

Users may choose to override the automatic synchronizer

by setting SYNC_MSYN = 1 and writing values manually

to SYNC_PS to set the phase of the internal multiplex-

er. When using SYNC_MSYN = 1, users must monitor

SYNC_PH and adjust SYNC_PS as needed according to

Table 6. For further details see the Synchronizing Multiple

LTC2000As section.

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