LTC2000 datasheet(37/54 Pages) LINER

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LTC2000A

2000afb

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APPLICATIONS INFORMATION

A more integrated clock source is one based on a low

phase noise, low jitter PLL. Figure 13 shows how the

DAC sample clock can be generated from the LTC6946,

a high performance PLL with an internal VCO that can

provide output frequencies from 0.37GHz to 5.7GHz. See

the LTC6946 data sheet for details.

Synchronizing Multiple LTC2000As in Dual-Port Mode

In some applications, it is necessary to synchronize mul-

tiple LTC2000As to each other such that related samples

arrive at all DAC outputs simultaneously. Figures 14 and

15a show a block diagram and sample waveforms for

such a system in which two DACs (X and Y) are to be

synchronized in dual-port mode.

Note that in this example a small timing skew between

the two data signals at the DCKIP/N pins of DACs X and

Y has caused the DCKIP/N rising edges to arrive on op-

posite sides of a DAC sample clock (CKP/N) rising edge,

and thus within different CKP/N clock cycles. As a result

the default behavior is for the output of DAC Y to update

with sample N one cycle earlier than the output of DAC X.

It is possible to correct this misalignment and synchro-

nize DACs X and Y by adjusting the clock synchronizer

settings to subtract one cycle of latency from DAC X, as

shown in the adjusted waveform at the bottom of Figure

15a. See the Clock Synchronizer section and Figure 7 for

more details on the operation of the clock synchronizer.

In order to synchronize multiple DACs as shown in Fig-

ures 14 and 15a, distribute the DAC sample clock carefully

with matched delays so that it arrives at the CKP/N pins of

all DACs simultaneously. Any remaining timing mismatch

between sample clocks will appear directly as mismatch in

the DAC output timing. Ensure that the timing mismatch

between LVDS data clock signals at the DCKIP/N pins of all

DACs is less than 0.4 cycles of the DAC sample clock, mi-

nus any timing mismatch between the DAC sample clocks.

Besuretomaintainsufficientmatchingbetweenthetiming

of the LVDS data inputs (DAP/N, DBP/N) and DCKIP/N for

each DAC to meet the setup and hold time specifications

(t11, t12) in the Timing Characteristics section.

For example, let us consider a system using multiple DACs

at 2.7Gsps in which the sample clock is designed to arrive

at the CKP/N pins of all DACs within 30ps of one another.

The sample clock period is 370ps, so the maximum allow-

able timing mismatch between the data clock signals at

the DCKIP/N pins of all DACs will be (0.4 • 370ps) – 30ps

= 118ps. For a system using multiple DACs at 1.35Gsps,

the allowable mismatch between DCKIP/N pins will be (0.4

• 740ps) – 30ps = 266ps. In both cases, once the DACs

÷N = 250

÷O = 1

N_DIV

÷R = 10

fPFD

REF±

(fREF)

fREF*

100pF

68nH

LTC6946

KPFD

fVCO

KVCO

ICP =

11.2mA

VRF+

LOOP FILTER

LF(s)

2000A F13

TUNE

453

100pF

0.022µF

R_DIV

O_DIV

RF±

*CRYSTEK CVHD-950-100.000 100MHz OSCILLATOR

RF+

RF–

(fRF)

2700pF

68nH

CKP

CKN

LTC2000A

Figure 13. DAC Sample Clock Generation with the LTC6946

Figure 12. DAC Sample Clock Generation with an

RF Signal Generator and a 1:1 Balun

•

100pF

LTC2000A F12

1nF

LTC2000A

MINI-CIRCUITS

TC1-1-13M

RF SIGNAL

GENERATOR

CKP

CKN

LTC2000 Datasheet(PDF) 37 Page - Linear Technology

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