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LTM9002 Datasheet(PDF) 1 Page - Linear Technology

Part # LTM9002
Description  Dual 12-Bit 310Msps ADC
PDF  28 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTM9002 Datasheet(HTML) 1 Page - Linear Technology

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215812fa
LTC2158-12
For more information www.linear.com/LTC2158-12
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Dual 12-Bit 310Msps ADC
n
Communications
n
Cellular Basestations
n
Software Defined Radios
n
Medical Imaging
n
High Definition Video
n
Testing and Measurement Instruments
n
67.6dBFS SNR
n
88dB SFDR
n
Low Power: 688mW Total
n
Single 1.8V Supply
n
DDR LVDS Outputs
n
1.32VP-P Input Range
n
1.25GHz Full Power Bandwidth S/H
n
Optional Clock Duty Cycle Stabilizer
n
Low Power Sleep and Nap Modes
n
Serial SPI Port for Configuration
n
Pin-Compatible 14-Bit Versions
n
64-Lead (9mm × 9mm) QFN Package
The LTC®2158-12 is a 2-channel simultaneous sampling
310Msps 12-bit A/D converter designed for digitizing high
frequency, wide dynamic range signals. It is perfect for
demanding communications applications with AC per-
formance that includes 67.6dB SNR and 88dB spurious
free dynamic range (SFDR). The 1.25GHz input bandwidth
allows the ADC to undersample high frequencies with
good performance. The latency is only six clock cycles.
DC specs include ±0.6LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.6LSBRMS.
The digital outputs are double data rate (DDR) LVDS.
The ENC+ and ENC– inputs can be driven differentially with
asinewave,PECL,LVDS,TTL,orCMOSinputs.Anoptional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
DA10_11
•
•
•
DA0_1
DB10_11
•
•
•
DB0_1
CLOCK
ANALOG
INPUT
215812 TA01
DDR
LVDS
DDR
LVDS
VDD
OVDD
OGND
OGND
GND
CHANNEL A
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
ANALOG
INPUT
OVDD
CHANNEL B
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
0
20
40
60
80
215812 TA10b
100
140
120
–20
LTC2158-12 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 310Msps


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