21

215812fa

LTC2158-12

For more information www.linear.com/LTC2158-12

REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

Bits 7-5

Unused Bit

Bits 4-2

ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 1

TERMON

LVDS Internal Termination Bit

0 = Internal Termination Off

1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0

Bit 0

OUTOFF

Digital Output Mode Control Bits

0 = Digital Outputs Are Enabled

1 = Digital Outputs Are Disabled (High Impedance)

REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)

D7

D6

D5

D4

D3

D2

D1

D0

OUTTEST2

OUTTEST1

OUTTEST0

ABP

0

DTESTON

RAND

TWOSCOMP

Bits 7-5

OUTTEST2:OUTTEST0

Digital Output Test Pattern Bits

000 = All Digital Outputs = 0

001 = All Digital Outputs = 1

010 = Alternating Output Pattern. OF, D11-D0 alternate between 0 0000 0000 0000 and 1 1111 1111 1111

100 = Checkerboard Output Pattern. OF, D11-D0 alternate between 1 0101 0101 0101 and 0 1010 1010 1010

Note 1: Other bit combinations are not used.

Note 2: Patterns from channel A and channel B may not be synchronous.

Bit 4

ABP

Alternate Bit Polarity Mode Control Bit

0 = Alternate Bit Polarity Mode Off

1 = Alternate Bit Polarity Mode On

Bit 3

Must Be Set to 0

Bit 2

DTESTON

Enable the digital output test patterns (set by Bits 7-5)

0 = Normal Mode

1 = Enable the Digital Output Test Patterns

Bit 1

RAND

Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

Bit 0

TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

APPLICATIONS INFORMATION