LTC2602 datasheet(10/26 Pages) LINER

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LTC2311-16

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PIN FUNCTIONS

GND(Pins1,5,8,11):Ground.Thesepinsandtheexposed

pad (Pin 17) must be tied directly to a solid ground plane.

REFIN (Pin 2): Reference Buffer 1.25V Input/Output. An

onboard buffer nominally outputs 1.25V to this pin. This

pin should be decoupled closely to the pin (no vias) with

a 10μF (X5R, 0805 size) ceramic capacitor. The internal

buffer driving this pin may be overdriven with an external

reference. The REFIN pin, when pulled to GND disables

the REFOUT pin buffer allowing an external reference to

drive REFOUT directly.

REFOUT (Pin 3): Reference Buffer Output. An onboard

buffernominallyoutputs4.096Vtothispin.Thispinshould

be decoupled closely to the pin (no vias) with a 10μF (X5R,

0805 size) ceramic capacitor. The internal buffer driving

this pin may be disabled by grounding the REFIN pin. If

the buffer is disabled, an external reference may drive this

pin in the range of 1.25V to VDD.

VDD (Pin 4): Power Supply. Bypass VDD to GND with a

1µF ceramic capacitor close to the VDD pin.

AIN+, AIN– (Pins 6, 7): Analog Differential Input Pins. Full-

scale range (AIN+ to AIN–) is ±REFOUT voltage. These pins

can be driven from VDD to GND.

CNV (Pin 9): Convert Input. This pin, when high, defines

the sampling phase. When this pin is driven low, the con-

version phase is initiated and output data is clocked out.

This input pin is a TTL style input typically driven at OVDD

levels with a low jitter pulse, but it is bound to VDD levels.

This pin is unaffected by the CMOS/LVDS pin.

CMOS/LVDS (Pin 10): I/O mode select. Ground this pin

to enable CMOS mode, tie to OVDD to enable LVDS mode.

Float this pin to enable low power LVDS mode.

OVDD (Pin 12): I/O Interface Digital Power. The range of

OVDD is 1.71V to 2.5V. This supply is nominally set to the

same supply as the host interface (CMOS: 1.8V or 2.5V,

LVDS: 2.5V). Bypass OVDD to GND with a 1μF ceramic

capacitor close to the OVDD pin.

Exposed Pad (Pin 17): Ground. Solder this pad to ground.

CMOS I/O Mode

SDO+ (Pin 14): Serial Data Output. The conversion result

is shifted MSB first on each falling edge of SCK. The result

is output on SDO+. The logic level is determined by OVDD.

Do not connect SDO–.

SCK+ (Pin 16): Serial Data Clock Input. The falling edge

of this clock shifts the conversion result MSB first onto

the SDO pins. Drive SCK+ with a single-ended clock. The

logic level is determined by OVDD. Do not connect SCK–.

LVDS I/O Mode

SDO+, SDO– (Pins 14, 13): Serial Data Output. The con-

version result is shifted MSB first on each falling edge of

SCK. The result is output differentially on SDO+ and SDO–.

These pins must be differentially terminated by an external

100Ω resistor at the receiver (FPGA).

SCK+, SCK– (Pins 16, 15): Serial Data Clock Input. The

falling edge of this clock shifts the conversion result MSB

first onto the SDO pins. Drive SCK+ and SCK– with a dif-

ferentialclock.Thesepinsmustbedifferentiallyterminated

by an external 100Ω resistor at the receiver (ADC).

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