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LTC2311-16

231116fa

For more information www.linear.com/LTC2311-16

DIGITAL INTERFACE

The LTC2311-16 features a serial digital interface that

is simple and straightforward to use. The flexible OVDD

supply allows the LTC2311-16 to communicate with any

digital logic operating between 1.8V and 2.5V. A 105MHz

external clock must be applied at the SCK pin to achieve

5Msps throughput.

In addition to a standard CMOS SPI interface, the

LTC2311-16 provides an optional LVDS SPI interface to

support low noise digital design. The CMOS/LVDS pin is

used to select the digital interface mode.

The falling edge of SCK outputs the conversion result MSB

first on the SDO pins. In CMOS mode, use the SDO+ pin

as the serial data output and the SCK+ pin as the serial

clock input. Do not connect the SDO– and SCK– pins as

they have internal pull-downs to GND.

In LVDS mode, use the SDO+/SDO– pins as a differential

output. These pins must be differentially terminated by an

external 100Ω resistor at the receiver (FPGA). The SCK+/

SCK– pins are a differential input and must be terminated

differentially by an external 100Ω resistor at the receiver

(ADC), see Figure 22.

BOARD LAYOUT

To obtain the best performance from the LTC2311-16, a

four layer printed circuit board is recommended. Layout

for the printed circuit board (PCB) should ensure the

digital and analog signal lines are separated as much as

possible. In particular, care should be taken not to run

any digital clocks or signals adjacent to analog signals or

underneath the ADC.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

Reference Design

Foradetailedlookatthereferencedesignforthisconverter,

including schematics and PCB layout, please refer to the

DC2425, the evaluation kit for the LTC2311-16.

APPLICATIONS INFORMATION

Figure 22. LTC2311-16 Using the LVDS Interface

2.5V

OVDD

LTC2311-16

FPGA OR DSP

231116 F22

SCK+

SCK–

SDO+

SDO–

CNV

CMOS/LVDS

–

100

–

100

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