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LTC2311-16

231116fa

For more information www.linear.com/LTC2311-16

APPLICATIONS INFORMATION

sampling capacitor in series with approximately 15Ω

(RON) from the on-resistance of the sampling switch is

connected to the input. Any unwanted signal that is com-

mon to both inputs will be reduced by the common mode

rejection of the ADC sampler. The inputs of the ADC core

draw a small current spike while charging the CIN capaci-

tors during acquisition.

Single-Ended Signals

Single-ended signals can be directly digitized by the

LTC2311-16. These signals should be sensed pseudo-

differentially for improved common mode rejection. By

connecting the reference signal (e.g., ground sense) of

the main analog signal to the other AIN pin, any noise or

disturbance common to the two signals will be rejected

by the high CMRR of the ADC. The LTC2311-16 flexibility

handles both pseudo-differential unipolar and bipolar sig-

nals, with no configuration required. The wide common

mode input range relaxes the accuracy requirements of

any signal conditioning circuits prior to the analog inputs.

Pseudo-Differential Bipolar Input Range

The pseudo-differential bipolar configuration represents

driving one of the analog inputs at a fixed voltage, typically

VREF/2, and applying a signal to the other AIN pin. In this

case the analog input swings symmetrically around the

fixedinputyieldingbipolartwo’scomplementoutputcodes

with an ADC span of half of full-scale. This configuration

is illustrated in Figure 4, and the corresponding transfer

function in Figure 5. The fixed analog input pin need not

be set at VREF/2, but at some point within the VDD rails

allowingthealternateinputtoswingsymmetricallyaround

thisvoltage.Iftheinputsignal(AIN+–AIN–)swingsbeyond

±REFOUT/2, valid codes will be generated by the ADC and

must be clamped by the user, if necessary.

Figure 4. Pseudo-Differential Bipolar Application Circuit

Figure 5. Pseudo-Differential Bipolar Transfer Function

47pF

VREF

VREF/2

VREF

10k

–

LTC2311-16

LT1819

231116 F04

SDO

REFIN

REFOUT

SCK

AIN–

AIN+

CNV

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

10µF

1µF

231116 F05

–VREF

–16385

16384

–32768

32767

VREF

DOTTED REGIONS AVAILABLE

BUT UNUSED

AIN

(AIN+ – AIN–)

ADC CODE

(2’s COMPLEMENT)

–VREF/2

VREF/2

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