LT6201 datasheet(18/22 Pages) LINER

18 / 22 page

LTC2385-18

238518f

For more information www.linear.com/LTC2385-18

APPLICATIONS INFORMATION

10µF ceramic capacitor in parallel. Bypass VDDL to GND

with a 0.1µF ceramic capacitor close to the pair of pins

and a 10µF ceramic capacitor in parallel. OVDD can come

from the same source as VDDL but it should be isolated

by a ferrite bead and have its own 0.1μF bypass capacitor.

Power Supply Sequencing

The LTC2385-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2385-18

has a power-on-reset (POR) circuit that will reset the

LTC2385-18 at initial power-up or whenever VDD or VDDL

drops well below their minimum values. Once the supply

voltage re-enters the nominal supply voltage range, the

POR will reinitialize the ADC.

Power-Down Mode

When PD is pulled low, LTC2385-18 enters power-down

mode. In this state, all internal functions, including the

referenceandLVDSoutputs,areturnedoffandsubsequent

conversion requests are ignored. The power consumption

drops to a typical value of 10µW. This mode can be used

if the LTC2385-18 is inactive for a long period of time and

the user wants to minimize power dissipation.

The amount of time required to recover from power-down

mode depends on how REFBUF is configured. When using

the internal reference buffer with a 10µF bypass capacitor,

the ADC will stabilize after 20ms. If REFBUF is externally

driven, the recovery time can be significantly less.

TIMING AND CONTROL

CNV Timing

The LTC2385-18 conversion is controlled by the CNV+ and

CNV– inputs. CNV+/CNV– can be driven directly with an

LVDS signal. Alternatively, CNV+ can be driven with a 0V

to 2.5V CMOS signal when CNV– is tied to GND. A rising

edge on CNV+ will sample the analog inputs and start a

conversion. The pulse width of CNV+ should meet the

tCNVH and tCNVL specifications in the timing table.

After the LTC2385-18 is powered on, or exits power-down

mode, conversion data is invalid for the first two conver-

sion cycles. Subsequent results are accurate as long as

thetimebetweenconversionsmeetsthetCYCspecification.

If the analog input signal has not completely settled when

it is sampled, the ADC noise performance will be affected

by jitter on the rising edge of CNV+. In this case the rising

edge of CNV+ should be driven by a clean low jitter signal.

Note that the ADC is less sensitive to jitter on the falling

edge of CNV+.

In applications that are insensitive to jitter, CNV can be

driven directly from an FPGA.

Internal Conversion Clock

The LTC2385-18 has an internal clock that is trimmed

to achieve a maximum conversion time of 101ns. With a

typicalacquisitiontimeof133ns,throughputperformance

of 5Msps is guaranteed.

DIGITAL INTERFACE

The LTC2385-18 has a serial LVDS digital interface that

is easy to connect to an FPGA. Three LVDS pairs are re-

quired: CLK±, DCO±, and DA±. A fourth LVDS pair, DB±,

is optional (Figure 11).

Figure 11. Digital Output Interface to an FPGA

238518 F11

LTC2385-18

OPTIONAL

FPGA

100

CLK+

CLK–

100

DCO+

DCO–

–

100

DA+

DA–

100

DB+

DB–

–

LT6201 Datasheet(PDF) 18 Page - Linear Technology

LT6201 Datasheet(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL