LT6237 datasheet(15/52 Pages) LINER

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LTC2373-16

237316fa

For more information www.linear.com/LTC2373-16

pin FuncTions

CH0 to CH7 (Pins 1, 2, 7, 8, 9, 10, 31 and 32): Analog

Inputs. CH0 to CH7 can be configured as single-ended

inputs relative to COM, or as pairs of differential input

channels. See the Analog Input Multiplexer section.

Unused analog inputs should be tied to a DC voltage within

the analog input voltage range of (GND – 0.3V) to (VDD +

0.3V) as specified in Absolute Maximum Ratings.

MUXOUT+, MUXOUT– (Pin 3, Pin 6): Analog Output Pins

of MUX.

ADCIN+, ADCIN– (Pin 4, Pin 5): Analog Input Pins of

ADC Core.

GND (Pins 11, 14, 15, 17, 23, 26, 27 and Exposed Pad

Pin 33): Ground.

REFBUF (Pin 12): Reference Buffer Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 47μF ceramic capacitor. The internal buffer

driving this pin may be disabled by grounding its input

at REFIN. Once the buffer is disabled, an external refer-

ence may overdrive this pin in the range of 2.5V to 5V.

A resistive load greater than 500k can be placed on the

reference buffer output.

REFIN (Pin 13): Reference Output/Reference Buffer In-

put. An onboard bandgap reference nominally outputs

2.048V at this pin. Bypass this pin with a 0.1μF ceramic

capacitor to GND to limit the reference output noise. If

more accuracy is desired, this pin may be overdriven by

an external reference in the range of 1.25V to 2.4V.

CNV (Pin 16): Convert Input. A rising edge on this input

powers up the part and initiates a new conversion. Logic

levels are determined by OVDD.

RDL (Pin 18): Read Low Input. When RDL is low, the serial

data I/O bus is enabled. When RDL is high, the serial data

I/O bus becomes Hi-Z. RDL also gates the external shift

clock. Logic levels are determined by OVDD.

BUSY (Pin 19): BUSY Indicator. Goes high at the start of

a new conversion and returns low when the conversion

has finished. Logic levels are determined by OVDD.

SDI (Pin 20): Serial Data Input. Data provided on this pin

in synchrony with SCK can be used to program the MUX

channel configuration, converter input range and digital

gain compression setting via the sequencer. Input data on

SDI is latched on rising edges of SCK when the serial data

I/O bus is enabled. Logic levels are determined by OVDD.

SCK (Pin 21): Serial Data Clock Input. When the serial

data I/O bus is enabled, the conversion result followed

by configuration information is shifted out at SDO on

the rising edges of this clock MSB first. Serial input data

is latched on the rising edges of this clock at SDI. Logic

levels are determined by OVDD.

SDO (Pin 22): Serial Data Output. The conversion result

followed by configuration information is output on this

pin on each rising edge of SCK MSB first when the serial

data I/O bus is enabled. The output data format is de-

termined by the converter operating mode. Logic levels

are determined by OVDD.

RESET(Pin24):ResetInput.Whenthispinisbroughthigh,

the LTC2373-16 is reset. If this occurs during a conver-

sion, the conversion is halted and the data bus becomes

Hi-Z. Logic levels are determined by OVDD.

OVDD (Pin 25): I/O Interface Digital Power. The range of

OVDD is 1.71V to 5.25V. This supply is nominally set to

the same supply as the host interface (1.8V, 2.5V, 3.3V,

or 5V). Bypass OVDD to GND with a 0.1μF capacitor.

VDDLBYP (Pin 28): 2.5V Supply Bypass Pin. The voltage on

this pin is generated via an onboard regulator off of VDD.

This pin must be bypassed with a 2.2μF ceramic capacitor

to GND. Applying an external voltage to this pin can cause

damage to the IC or improper operation.

VDD (Pin 29): 5V Power Supply. The range of VDD is 4.75V

to5.25V.BypassVDDtoGNDwitha10µFceramiccapacitor.

COM (Pin 30): Common Input. This is the reference point

for all single-ended inputs. It must be free of noise and

connected to GND for unipolar conversions and REFBUF/2

for bipolar conversions. If unused, this input should be

tied to a DC voltage within the analog input voltage range

of (GND – 0.3V) to (VDD + 0.3V) as specified in Absolute

Maximum Ratings.

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