LTC4211 datasheet(18/22 Pages) LINER

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LTC4235

4235f

For more information www.linear.com/LTC4235

applicaTions inForMaTion

Ascanbeseen,theLTC4235’sfoldbackcurrentlimitprofile

roughly coincides with the 100ms SOA contour. Since

this SOA plot is for an ambient temperature of 25°C only,

a maximum fault timer period of much less than 100ms

should be considered, such as 10ms or less. Selecting a

0.1µF ±10% value for CFT yields a maximum fault timer

period of1.75mswhichshouldbesmallenoughtoprotect

the MOSFET during any overcurrent fault scenario.

Next, select the values for the resistive divider at the ON

pin that defines the undervoltage threshold of 9.7V for the

12V supply at SENSE+. Since the leakage current for the

ON pin can be as high as ±1µA, the total resistance in the

divider should be low enough to minimize the resulting

offset error. Calculate the bottom resistor R1 based on

the following equation to obtain less than ±0.2% error

due to leakage current.

R1=

VON(TH)

IIN(LEAK)

⎛

⎝

⎜

⎞

⎠

⎟ • 0.2% =

1.235V

1µA

⎛

⎝⎜

⎞

⎠⎟

• 0.2% = 2.4k

Choose R1 to be 2k to achieve less than ±0.2% error and

calculating R2 yields:

R2 =

VIN(UV)

VON(TH)

– 1

⎛

⎝

⎜

⎞

⎠

⎟ • R1

R2 =

9.7V

1.235V

– 1

⎛

⎝⎜

⎞

⎠⎟

• 2k = 13.7k

The final components to consider are a 0.1µF bypass (C1)

at the INTVCC pin and a 0.1µF capacitor (C4) connected

between the REG and SENSE+ pins.

•••

•

••

•

PowerPAK SO-8

MD1

PowerPAK SO-8

MD2

PowerPAK SO-8

IN1

VIA TO IN1

CURRENT FLOW

TO LOAD

4235 F08

20 19 18 17

9 10

LTC4235UFD

OUT

IN2

CURRENT FLOW

TO LOAD

TRACK WIDTH W:

0.03" PER AMPERE

ON 1oz Cu FOIL

VIA TO C2 (CPO1)

VIA TO DGATE2

VIA TO SENSE+

VIA TO GND PLANE

VIA TO DGATE1

VIA TO C4 (REG)

Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistor

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