LTC6652 datasheet(7/50 Pages) LINER

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LTC2373-18

237318f

For more information www.linear.com/LTC2373-18

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above VDD or

OVDD, they will be clamped by internal diodes. This product can handle

input currents up to 100mA below ground or above VDD or OVDD without

latchup.

Note 4: VDD = 5V, OVDD = 2.5V, fSMPL = 1MHz, REFIN = 2.048V unless

otherwise noted.

Note 5: Recommended operating conditions.

Note 6: Guaranteed by design, not subject to test.

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Fully differential zero-scale error is the offset voltage measured

from –0.5LSB when the output code flickers between 01 1111 1111 1111

1111 and 10 0000 0000 0000 0000 in straight binary format and 00 0000

0000 0000 0000 and 11 1111 1111 1111 1111 in two’s complement

format. Unipolar zero-scale error is the offset voltage measured from

0.5LSB when the output code flickers between 00 0000 0000 0000 0000

and 00 0000 0000 0000 0001. Bipolar zero-scale error is the offset volt-

age measured from –0.5LSB when the output code flickers between 00

0000 0000 0000 0000 and 11 1111 1111 1111 1111. Fully differential full-

scale error is the worst-case deviation of the first and last code transitions

from ideal and includes the effect of offset error. Unipolar full-scale error

is the deviation of the last code transition from the ideal and includes the

effect of offset error. Bipolar full-scale error is the worst-case deviation

of the first and last code transitions from ideal and includes the effect of

offset error.

Note 9: When REFBUF is overdriven, the internal reference buffer must be

turned off by setting REFIN=0V.

Note 10: All specifications in dB are referred to a full-scale ±VREFBUF (fully

differential), 0V to VREFBUF (pseudo-differential unipolar), or ±VREFBUF/2

(pseudo-differential bipolar) input.

Note 11: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 12: fSMPL = 1MHz, IREFBUF varies proportionally with sample rate.

Note 13: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V

and OVDD = 5.25V.

Note 14: tSCK of 10ns maximum allows a shift clock frequency up to

100MHz for rising edge capture.

Figure 1. Voltage Levels for Timing Specifications

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

elecTrical characTerisTics

0.8 • OVDD

0.2 • OVDD

50%

237318 F01

0.2 • OVDD

0.8 • OVDD

0.2 • OVDD

0.8 • OVDD

tDELAY

tWIDTH

tDELAY

tSCK

SCK Period

(Notes 13, 14)

tSCKH

SCK High Time

tSCKL

SCK Low Time

tSSDISCK

SDI Setup Time From SCK

↑

(Note 13)

tHSDISCK

SDI Hold Time From SCK

↑

(Note 13)

tDSDO

SDO Data Valid Delay from SCK

↑

CL = 20pF, OVDD = 5.25V

CL = 20pF, OVDD = 2.5V

CL = 20pF, OVDD = 1.71V

7.5

9.5

tHSDO

SDO Data Remains Valid Delay from SCK

↑

CL = 20pF (Note 6)

tDSDOBUSYL

SDO Data Valid Delay from BUSY

↓

CL = 20pF (Note 6)

tEN

Bus Enable Time After RDL

↓

(Note 13)

tDIS

Bus Relinquish Time After RDL

↑

(Note 13)

tWAKE

REFBUF Wake-Up Time

CREFBUF = 47μF, CREFIN = 0.1µF

200

tCNVMRST

CNV

↑ to MUX Starts Resetting Delay

tMRST1

MUX Reset Time During Conversion

tVLDMRST

8th SCK

↑ to MUX Starts Resetting Delay After

Programming 1st Valid Configuration Word

tMRST2

MUX Reset Time During Acquisition After

Programming 1st Valid Configuration Word

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