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LTC2373-18

237318f

For more information www.linear.com/LTC2373-18

applicaTions inForMaTion

OVERVIEW

The LTC2373-18 is a low noise, high speed, highly con-

figurable 8-channel 18-bit successive approximation

crosstalk 8-channel input multiplexer (MUX) and a high

performance 18-bit accurate ADC core that can be con-

figured to accept fully-differential, pseudo-differential

unipolar and pseudo-differential bipolar input signals. The

input range of the ADC core can be set independently of

the MUX input channel configuration. The outputs of the

MUX and inputs of the ADC core are pinned out, allowing

flexibility in how the MUX is connected to the ADC core.

The MUX may be wired directly to the ADC core or signal

conditioning circuitry may be inserted between the MUX

andADCcore,dependingontheapplication.TheLTC2373-

18 also has a selectable digital gain compression (DGC)

feature. The LTC2373-18 has a programmable sequencer

that can be programmed with configuration words

ranging from a depth of one up to a maximum depth of

16 configuration words.

The LTC2373-18 has an onboard low drift reference and

a single-shot capable reference buffer. The LTC2373-18

also has a high speed SPI-compatible serial interface that

supports 1.8V, 2.5V, 3.3V and 5V logic. The LTC2373-

18 automatically naps between conversions, leading to

reduced power dissipation that scales with the sampling

rate. A sleep mode is also provided for further power

savings during inactive periods.

CONVERTER OPERATION

The LTC2373-18 operates in two phases. During the ac-

quisition phase when MUXOUT+/– is wired to ADCIN+/–,

the charge redistribution capacitor D/A converter (CDAC)

is connected through the MUX to the selected MUX

analog input pins. A rising edge on the CNV pin initiates

a conversion. During the conversion phase, the 18-bit

CDAC is sequenced through a successive approximation

algorithm, effectively comparing the sampled input with

binary-weighted fractions of the reference voltage (e.g.

VREFBUF/2, VREFBUF/4 … VREFBUF/262144) using a dif-

ferential comparator. At the end of conversion, the CDAC

output approximates the sampled analog input. The ADC

control logic then prepares the 18-bit digital output code

for serial transfer.

Figure 2. LTC2373-18 Two’s Complement Transfer Function.

Straight Binary Transfer Function Can Be Obtained by Inverting

the Most Significant Bit (MSB) of Each Output Code

TRANSFER FUNCTION

The LTC2373-18 digitizes the full-scale voltage of 2 ×

REFBUF in fully differential mode and REFBUF in pseudo-

differential mode into 218 levels. With REFBUF = 4.096V,

the resulting LSB sizes in fully differential and pseudo-

differentialmodesare31.25μVand15.625μV,respectively.

The binary format of the conversion result depends on the

converter input range as described in Table 6. The ideal

two’s complement transfer function is shown in Figure 2,

while the ideal straight binary transfer function is shown in

Figure 3. The ideal straight binary transfer function can be

obtained from the two’s complement transfer function by

invertingthemostsignificantbit(MSB)ofeachoutputcode.

Figure 3. LTC2373-18 Straight Binary Transfer Function

INPUT VOLTAGE (V)

–1

LSB

237318 F02

011...111

011...110

000...001

000...000

100...000

100...001

111...110

LSB

BIPOLAR

ZERO

111...111

FSR/2 – 1LSB

–FSR/2

FSR = +FS – –FS

1LSB = FSR/262144

INPUT VOLTAGE (V)

237318 F03

111...111

111...110

100...001

100...000

000...000

000...001

011...110

UNIPOLAR

ZERO

011...111

FSR – 1LSB

FSR = +FS

1LSB = FSR/262144

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