LT6237 datasheet(29/50 Pages) LINER

29 / 50 page

LTC2373-18

237318f

For more information www.linear.com/LTC2373-18

POWER CONSIDERATIONS

The LTC2373-18 provides two power supply pins: the 5V

power supply (VDD), and the digital input/output interface

power supply (OVDD). The flexible OVDD supply allows the

LTC2373-18tocommunicatewithanydigitallogicoperating

between 1.8V and 5V, including 2.5V and 3.3V systems.

Power Supply Sequencing

The LTC2373-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2373-18

has a power-on-reset (POR) circuit that will reset the

LTC2373-18 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 100ms after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

TIMING AND CONTROL

CNV Timing

The LTC2373-18 conversion is controlled by CNV. A ris-

ing edge on CNV will start a conversion and power up the

LTC2373-18.Onceaconversionhasbeeninitiated,itcannot

berestarteduntiltheconversioniscomplete.Foroptimum

performance, CNV should be driven by a clean low jitter

signal. Converter status is indicated by the BUSY output

which remains high while the conversion is in progress.

To ensure that no errors occur in the digitized results, any

additional transitions on CNV should occur within 40ns

from the start of the conversion or after the conversion

has been completed. Once the conversion has completed,

the LTC2373-18 powers down and begins acquiring the

input signal. It is not necessary to clock out all of the data

and configuration bits before starting a new conversion.

Internal Conversion Clock

The LTC2373-18 has an internal clock that is trimmed to

achieveamaximumconversiontimeof527ns.Withamini-

applicaTions inForMaTion

mum acquisition time of 460ns, throughput performance

of 1Msps is guaranteed without any external adjustments.

Auto Nap Mode

The LTC2373-18 automatically enters nap mode after a

conversion has been completed and completely powers

up once a new conversion is initiated on the rising edge of

CNV. During nap mode, only the ADC core powers down

and all other circuits remain active. During nap, data from

the last conversion can be clocked out. The auto nap mode

featurewillreducethepowerdissipationoftheLTC2373-18

as the sampling frequency is reduced. Since full power is

consumed only during a conversion, the ADC core of the

LTC2373-18remainspowereddownforalargerfractionof

the conversion cycle (tCYC) at lower sample rates, thereby

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 16.

Sleep Mode

The auto nap mode feature provides limited power savings

since only the ADC core powers down. To obtain greater

power savings, the LTC2373-18 provides a sleep mode.

During sleep mode, the entire part is powered down

except for a small standby current resulting in a power

dissipation of 300μW. To enter sleep mode, toggle CNV

twice with no intervening rising edge on SCK. The part

will enter sleep mode on the falling edge of BUSY from

the last conversion initiated. Once in sleep mode, a rising

Figure 16. Power Supply Current of the LTC2373-18 vs

Sampling Rate

SAMPLING FREQUENCY (kHz)

237318 F16

0 100 200 300 400 500 600 700 800 900 1000

IVDD

IOVDD

LT6237 Datasheet(PDF) 29 Page - Linear Technology

LT6237 Datasheet(HTML) 29 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL