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LTC7106

Rev A

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Table 4. LTC7106 Supported PMBus Commands

PMBus CODE

(8 BITS)

R/W TYPE

COMMAND NAME

DESCRIPTION

0x01

R/W

OPERATION

Default is On: [7:0] = 0x80

0x78

R/W

STATUS_BYTE

Read Fault Status: CML, Write 1 to Reset

0x98

Read

PMBUS_REVISION

Read PMBus Revision = 0x22 for Rev 1.2

0xE2

R/W

MFR_CHIP_CTRL

[7:4] – Reserved: [7:0] = 0x00 Default

[0] = GPO EN, [1] = Reserved, [2] = Write Protect, [3] = Timeout Status

0xE4

R/W

MFR_DAC_CTRL

[7:6] = Current Step Control, [5:0] = DAC Slew Rate Control

0xE5

R/W

MFR_IOUT_MARGIN_HIGH Same Format as MFR_IOUT_COMMAND

0xE6

R/W

MFR_IOUT_MAX

Clamped Value that DAC Cannot Exceed. Default 7-Bit Value of 0x00 = Source

Current Only

0xE7

Read

MFR_SPECIAL_ID

MFR Special ID for LTC7106 = 0x8080

0xE8

R/W

MFR_IOUT_COMMAND

IOUT Margining Command (see Table 5)

[5:0] Step Value, Source: [6] = 0, Sink: [6] = 1

0xED

R/W

MFR_IOUT_MARGIN LOW

Same Format as MFR_IOUT_COMMAND

0xFA

R/W

MFR_RAIL_ADDRESS

Set Common PMBus Address [6:0],

[7] = 0 Enable, [7] = 1 Disable

0xFD

Write

MFR_RESET

Reset PMBus Interface to Power-On State

Write Data is Ignored; 0, 1, 2 Bytes

MFR_IOUT_COMMAND

The DAC output current command is formatted as a 7-bit

2’s complement value. When the operation register is set

to 0x80, DAC takes the value stored in this register. Setting

bit[6] to 0 sources the current from the IC and bit[6] to 1

sinks the current into the IC. Default value for this register

is 0x00. The valid range of values are from 0x40 to 0x3F.

Do not attempt to write values outside of this range or

undesired behavior may result. Writes to this register are

inhibited when the WPB, bit [2] in MFR_CHIP_CTRL, is

set high.

MFR_IOUT_MARGIN_HIGH

DAC margining register with the same format and rules

as MFR_IOUT_COMMAND. The DAC value will take the

value stored in this register when the operation register

is set to margin high, 0xA8.

MFR_IOUT_MARGIN_LOW

DAC margining register with the same format and rules

as MFR_IOUT_COMMAND. The DAC value will take the

value stored in this register when the operation register

is set to margin low, 0x98.

MFR_IOUT_MAX

Clamping value that DAC cannot exceed. The format is

a 7-bit 2’s complement value, the same as the margin

registers. Therefore, the DAC value cannot be a smaller

2’s complement value than what is stored in this register.

The 7-bit default value is 0x00 = cannot sink current. IOUT

cannot be set to a higher value unless this value is changed

to a negative number, bit [7] = 1.

Setting this register to 0x40 allows the LTC7106 to sink

the maximum current with no clamping.

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