PEF24902 datasheet(21/52 Pages) INFINEON

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PEB 24902

PEF 24902

Functional Description

Data Sheet

Rev. 1, 2004-05-28

3.2

Clock Generation

All timing signals are derived from a 15.36 MHz system clock. The 15.36 MHz clock can

be provided by the IEC-4-AFE-X Version 3.2 by a crystal based PLL, which is

synchronized to either an 8 kHz or a 2048 kHz clock at pin CLOCK. The frequency at pin

CLOCK is detected automatically.

The PLL is set to the nominal frequency either by a POR or by a falling edge at the RES

pin. When the reference clock (CLOCK) is applied, the PLL starts to synchronize.

The 15.36 MHz clock can also be provided externally at pin CL15 without making use of

the internal PLL. In this mode the pin XIN must be tied to either VDD or GND. An internal

power-on-reset circuitry assures that the pin CL15 is an input until a 15.36 MHz clock is

detected at the output of the PLL/oscillator.

To enable error-free data transport to/from the Quad IEC DFE-T/Q, the clocks DCL and

FSC from the IOM®-2-interface must be synchronous to the 15.36 MHz signal. Therefore

it is recommended to use the same signal for FSC and as input to CLOCK pin at the IEC-

4-AFE-X Version 3.2 when the internal PLL is used to generate the 15.36 MHz clock.

If another clock source is used for CLOCK, e.g. the 2048 kHz DCL, a common time base

must be guaranteed. This is usually achieved if FSC is derived from DCL by dividing it

directly by 256.

Any constant phase difference between the time bases of both clocks is possible, but the

devices have currently been qualified and released only for using the same FSC signal

for the Quad IEC DFE-T/Q and for IEC-4-AFE-X Version 3.2.

3.2.1

Specification of the PLL and the 15.36 MHz Master Clock (Pin

CL15)

The PLL is based on a crystal connected to the pins XIN and XOUT. For synchronization

of the 15.36 MHz clock up to 16 internal capacitances are connected to XIN and XOUT.

The loop filter of the PLL is of second order, therefore a sinusoidal input jitter with the

angular frequency

ω = 2πf at CLOCK is attenuated by the PLL according to the following

formula:

H(j

ω) = [(2δ/ω

r)jω + 1] / [(jω/ωr)

2 + (2δ/ω

r)jω + 1]

H(j

ω) is the complex jitter transfer factor

r = 2πfr is the angular resonance frequency of the PLL

δ is the damping factor of the PLL

The maximum phase difference between the external CLOCK and the internal reference,

derived from the master clock, due to a sinusoidal input jitter with the angular frequency

ω is given as 1 - H(jω). The magnitude of the jitter transfer function and of the phase

difference are illustrated below:

PEF24902 Datasheet(PDF) 21 Page - Infineon Technologies AG

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