PEF22504HT datasheet(12/255 Pages) INFINEON

12 / 255 page

QuadLIU

PEF 22504

Introduction

Data Sheet

Rev. 1.3, 2006-01-25

Introduction

The QuadLIU

TM is the latest addition to Infineon’s family of sophisticated E1/T1/J1 Line interface Components.

This monolithic four channel device is designed to fulfill all required interfacing between four analog E1/T1/J1 lines

and four digital framer interfaces for world market telecommunication systems.

The device is supplied in P/PG-LBGA-160-1 package (P/PG-LBGA-160-1 is RoHS compliant) and in a PG-TQFP-

144-17 package, and is designed to minimize the number of external components required, so reducing system

costs and board space.

Due to its multitude of implemented functions, it fits to a wide range of networking applications and fulfills the

according international standards.

Crystal-less jitter attenuation with only one master clock source reduces the amount of required external

components.

Equipped with a flexible microprocessor interface, a SCI and a SPI interface, it connects to various control

processor environment. A standard boundary scan interface is provided to support board level testing. LBGA

device packaging, minimum number of external components and low power consumption lead to reduced overall

system costs.

The QuadLIU

TM is not hardware and software compatibel to older versions!

Other members of the FALC

® family are the OctalLIUTM supporting eight line interface components on a single

chip, the OctalFALC

TM and the QuadFALC® E1/T1/J1 Framer And Line interface Components for long-haul and

short-haul applications, supporting 8 or 4 channels on a single chip respectively.

PEF22504HT Datasheet(PDF) 12 Page - Infineon Technologies AG