PEF82913 datasheet(91/240 Pages) INFINEON

91 / 240 page

PEF 82912/82913

Functional Description

Data Sheet

2001-03-30

However, if the same filter is selected towards the state machine as programmed

towards the µC, the user has to be aware that if CRC mode is active, the state machine

is informed at the end of the next U-superframe.

2.4.5

M4, M5, M6 Bit Control Mechanisms

Figure 42 and Figure 43 show the control mechanisms that are provided for M4, M5 and

M6 bit data:

Via the M4WMASK register the user can selectively program which M4 bits are

externally controlled and which are set by the internal state machine or dedicated pins

(PS1, PS2). If one M4WMASK bit is set to ’0’ then the M4 bit value in the U-transmit

frame is determined by the bit value at the corresponding bit position in the M4W register.

Note: By bit 6 in the M4WMASK register it can be selected whether SAI is set by the

state machine or by µC access and whether the value of the received UOA bit is

reported to the state machine or UOA= ’1’ is signalled.

Via the M4RMASK register the user can selectively program which M4 bit changes shall

cause an report to the µC.

The M4W register latches the M4 bits that are sent with the next available U-superframe.

The M4R register contains the last validated M4 bit data.

The default value of M51, M52 and M61 can be overwritten at any time by use of register

M56W. M56R latches the last received and verified M5, M6 bit data.

The control of the FEBE bit is performed by the CRC-Processor, see Chapter 2.4.6.

PEF82913 Datasheet(PDF) 91 Page - Infineon Technologies AG