ISL6402

FN9123 Rev 3.00

Page 16 of 19

Nov 8, 2004

Component Selection Guidelines

MOSFET Considerations

The logic level MOSFETs are chosen for optimum efficiency

given the potentially wide input voltage range and output

power requirements. Two N-Channel MOSFETs are used in

each of the synchronous-rectified buck converters for the

PWM1 and PWM2 outputs. These MOSFETs should be

and thermal management considerations.

The power dissipation includes two loss components;

conduction loss and switching loss. These losses are

distributed between the upper and lower MOSFETs

according to duty cycle (see the following equations). The

conduction losses are the main component of power

dissipation for the lower MOSFETs. Only the upper MOSFET

has significant switching losses, since the lower device turns

on and off into near zero voltage. The equations assume

linear voltage-current transitions and do not model power

loss due to the reverse-recovery of the lower MOSFET’s

body diode.

which increases the upper MOSFET switching losses.

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal-resistance specifications.

Output Capacitor Selection

The output capacitors for each output have unique

requirements. In general, the output capacitors should be

selected to meet the dynamic regulation requirements

including ripple voltage and load transients. Selection of

output capacitors is also dependent on the output inductor,

so some inductor analysis is required to select the output

capacitors.

One of the parameters limiting the converter’s response to a

load transient is the time required for the inductor current to

slew to it’s new level. The ISL6402 will provide either 0% or

71% duty cycle in response to a load transient.

The response time is the time interval required to slew the

inductor current from an initial current value to the load

current level. During this interval the difference between the

inductor current and the transient current level must be

supplied by the output capacitor(s). Minimizing the response

time can minimize the output capacitance required. Also, if

the load transient rise time is slower than the inductor

response time, as in a hard drive or CD drive, it reduces the

requirement on the output capacitor.

The maximum capacitor value required to provide the full,

rising step, transient load current during the response time of

the inductor is:

drop in output voltage allowed during the load transient.

High frequency capacitors initially supply the transient

current and slow the load rate-of-change seen by the bulk

capacitors. The bulk filter capacitor values are generally

determined by the ESR (Equivalent Series Resistance) and

voltage rating requirements as well as actual capacitance

requirements.

The output voltage ripple is due to the inductor ripple current

and the ESR of the output capacitors as defined by:

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load

circuitry for specific decoupling requirements.

Use only specialized low-ESR capacitors intended for

switching-regulator applications at 300kHz for the bulk

capacitors. In most cases, multiple small-case electrolytic

capacitors perform better than a single large-case capacitor.

The stability requirement on the selection of the output

30kHz. This range is set by an internal, single compensation

zero at 6kHz. The ESR zero can be a factor of five on either

side of the internal zero and still contribute to increased

phase margin of the control loop. Therefore,

In conclusion, the output capacitors must meet three criteria:

1. They must have sufficient bulk capacitance to sustain the

output voltage during a load transient while the output

inductor current is slewing to the value of the load

transient,

2. The ESR must be sufficiently low to meet the desired

output voltage ripple due to the output inductor current,

and

3. The ESR zero should be placed, in a rather large range,

to provide additional phase margin.

2

 r

DS ON



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OUT

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 V

IN

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SW

 F

SW

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2

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2

 r

DS ON

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 V

IN

–

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 I

TRAN

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2

–

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OUT

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1

2

 ESR

 f

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-------------------------------------

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