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April 10, 2001

79RC5000

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The RC5000 serves many performance critical embedded applica-

tions, such as high-end internetworking systems, color printers, and

graphics terminals.

The RC5000 is optimized for high-performance applications, with

special emphasis on system bandwidth and floating point operations,

through integration of high-performance computational units and a high-

performance memory hierarchy. For this class of application, the result

is a relatively low-cost CPU capable of approximately 330 Dhrystone

MIPS.

IDT’s objectives in offering the RC5000 include:

customers in the internetworking, office automation and

visualization markets.

performance currently available in a moderately priced MIPS

CPU.

systems by using large primary caches and integrating a

secondary cache controller.

MIPS-IV ISA.

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The RC5000 recognizes two general classes of instructions for multi-

issue:

These instruction classes are pre-decoded by the RC5000, as they

are brought on-chip. The pre-decoded information is stored in the

instruction cache.

Assuming that there are no pending resource conflicts, the RC5000

can issue one instruction per class per pipeline clock cycle. Note that

this broad separation of classes insures that there are no data depen-

dencies to restrict multi-issue.

However, long-latency resources in either the floating-point ALU (e.g.

DIV or SQRT instructions) or instructions in the integer unit (such as

multiply) can restrict the issue of instructions. Note that the R5000 does

not perform out-of-order or speculative execution; instead, the pipeline

slips until the required resource becomes available.

There are no alignment restrictions on dual-issue instruction pairs.

The RC5000 fetches two instructions from the cache per cycle. Thus, for

optimal performance, compilers should attempt to align branch targets

to allow dual-issue on the first target cycle, since the instruction cache

only performs aligned fetches.

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The RC5000 implements the MIPS-IV 64-bit ISA, including CP1 and

CP1X functional units (and their instruction set).

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The RC5000 is a limited dual-issue machine that utilizes a traditional

5-stage integer pipeline. This basic integer pipeline of the RC5000 is

illustrated in Figure 1. The integer instruction execution speed is tabu-

lated (in number of pipeline clocks) as follows:

The RC5000’s short pipeline keeps the load and branch latencies

very low. The caches contain special logic that allows any combination

of loads and stores to execute in back-to-back cycles without requiring

pipeline slips or stalls. (This assumes that the operation does not miss

in the cache.)

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Store

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MULT/MULTU

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DMULT/DMULTU

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DIV/DIVU

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DDIV/DDIVU

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68

Other Integer ALU

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Branch

2

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Table 1 Integer Instruction Execution Speed