AV2636

Product Datasheet

1/fs

n-1 n-2

1

0

n-1 n-2

1

0

Right Channel

Left Channel

SF

SC

SD

1 SC

1 SC

MSB

LSB

MSB

LSB

RIGHT JUSTIFIED MODE

In right justified mode, the serial interface accepts input data at SD pin and frame input at SF pin.

The serial data is time multiplexed with the frame signal SF indicating left and right channel data.

SF is high during left channel data and low during right channel data. The SF is also a timing

signal for the end of each word of left and right channel.

The MSB is received first and LSB is aligned with the transition of frame signal SF. Data is

sampled at the rising edge of SC. Word lengths of 16/18/20/24 bits are supported.

1/fs

n-1 n-2

1

0

n-1 n-2

1

0

Right Channel

Left Channel

SF

SC

SD

MSB

LSB

MSB

LSB

DSP MODE

In DSP mode, the serial interface accepts input data at SD pin and frame input at SF pin. Audio

data SD is time multiplexed with left channel first followed by right channel data. Frame sync SF

appears every 1/fs time. Minimum SF pulse high is 1 SC cycle and maximum SF pulse high is 8

SC cycles. Both DSP ‘early’ mode and ‘late’ mode are supported.

The MSB is received first. Data is sampled at the rising edge of SC. Word lengths of 16/18/20/24

bits are supported.

AVS Technology, Inc.

7-16

August 18, 2004

www.avstech.com