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AV2636 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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AV2636 Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 16 page ![]() AV2636 Product Datasheet SERIAL CONTROL INTERFACE The AV2636 supports a 2-wire I 2C compatible serial control interface. When MODE pin is externally pulled high, the FMTC and FMTD pins function as SCL and SDA. Where SCL is serial clock input and SDA is serial data input and output. The internal control registers can be programmed through the interface. The chip ID for the AV2636 is a 7-bit hexadecimal number “32hex”. The protocol for write operation consists of sending 3 bytes of data to the AV2636 at SDA pin. Following each byte is the acknowledge bit generated by the AV2636. The first byte is the 7-bit chip ID followed by the read/write bit (read is logic high and write is logic low). The second byte is control register address. The third byte is control register data. The following diagram shows a “write” sequence and timing of control register address 00H and data 30H. SDA SCL START CA6 CA0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP 0 1 1 0 0 1 1 Chip ID: CA[6:0] = 0110010 Register Address: A[7:0] = 00H Data: D[7:0] = 30H Timing specifications tBF STOP START STOP tDH_STA tLOW tr tf tHIGH tDH_DA tDS_DA tDS_STO START tDS_STA SDA SCL Symbol Descriptions Min Max Units fSC SCL clock frequency 100 kHz tDS_STA START condition SDA setup time 4.7 µs tDH_STA START condition SDA hold time 4.0 µs tDS_STO STOP condition SDA setup time 4.0 µs tLOW SCL low pulse time 4.7 µs tHIGH SCL high pulse time 4.0 µs tr SCL and SDA rise time 1.0 µs tf SCL and SDA fall time 0.3 µs tDS_DA Data setup time 250 ns tDH_DA Data hold time 0 ns tBF Bus free time 4.7 µs AVS Technology, Inc. 9-16 August 18, 2004 www.avstech.com |
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