MAX30003 datasheet(21/46 Pages) MAXIM

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The latency of the R-to-R value written to the RTOR

Interval Memory Register is the sum of the R-to-R

decimation delay and the R-to-R detection delay blocks.

The R-to-R decimation factor is fixed at 256 and the

decimation delay (tR2R_DEC) is always 3,370 FMSTR

clocks, as shown in Table 6.

The detection circuit consists of several digital filters

and signal processing delays. These depend on the

WNDW[3:0] bits in the CNFG_RTOR (0x1D) register. The

detection delay (tR2R_DET) is described by the following

equation:

tR2R_DET = 5,376 + 256 x WNDW in FMSTR clocks

where WNDW is an integer from 0 to 15 and the total

latency (tR2R_DEL) is the sum of the two delays and

summarized in the equation below:

tR2R_DEL = tR2R_DEC + tR2R_DET = 3,370 + 5,376 +

256 x WNDW in FMSTR clocks where WNDW

is an integer from 0 to 15.

The total R-to-R latency minus the ECG latency is delay of

the R-to-R value relative to the ECG data and can be used

to place the first R-to-R value on the ECG data plot. The

succeeding values in the R-to-R Interval Memory Register

can be used as is to locate subsequent R-to-R values on

the ECG data plot relative to the initial placement.

Reference and Common Mode Buffer

The MAX30003 features internally generated reference

voltages. The bandgap output (VBG) pin requires an

external 1.0µF capacitor to AGND and the reference

output (VREF) pin requires a 10µF external capacitor to

AGND for compensation and noise filtering.

A common-mode buffer is provided to buffer 650mV

which is used to drive common mode voltages for internal

blocks. Use a 10µF external capacitor between VCM to

AGND to provide compensation and noise filtering.

SPI Interface Description

32 Bit Normal Mode Read/Write Sequences

The MAX30003 interface is SPI/QSPI/Micro-wire/DSP

compatible. The operation of the SPI interface is shown

in Figure 1. Data is strobed into the MAX30003 on SCLK

rising edges. The device is programmed and accessed by

a 32 cycle SPI instruction framed by a CSB low interval.

The content of the SPI operation consists of a one byte

command word (comprised of a seven bit address and a

Read/Write mode indicator, i.e., A[6:0] + R/W) followed by

a three-byte data word. The MAX30003 is compatible with

CPOL = 0/CPHA = 0 and CPOL = 1/CPHA = 1 modes of

operation.

Write mode operations will be executed on the 32nd SCLK

rising edge using the first four bytes of data available.

In write mode, any data supplied after the 32nd SCLK

rising edge will be ignored. Subsequent writes require CSB

to de-assert high and then assert low for the next write

command. In order to abort a command sequence, the

rise of CSB must precede the updating (32nd) rising-edge

of SCLK, meeting the tCSA requirement.

Read mode operations will access the requested data

on the 8th SCLK rising edge, and present the MSB of

the requested data on the following SCLK falling edge,

allowing the µC to sample the data MSB on the 9th SCLK

rising edge. Configuration, Status, and FIFO data are all

available via normal mode read back sequences. If more

than 32 SCLK rising edges are provided in a normal read

sequence then the excess edges will be ignored and the

device will read back zeros.

Table 6. R to R Decimation Delay in ms and FMSTR CLK vs. Register Settings,

FCLK = 32.768Hz

MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

www.maximintegrated.com

Maxim Integrated │ 21

FMSTR

[1:0]

FMSTR FREQ

IN FCLKs

FMSTR

FREQ (Hz)

DECIMATION

RTOR TIME

RESOLUTION (ms)

DELAY IN R TO R DECIMATION

IN FMSTR CLKs

IN ms

FCLK

32,768

256

7.8125

3370

102.844

FCLK x 625/640

32,000

256

8.0

3370

105.313

FCLK x 625/640

32,000

256

8.0

3370

105.313

FCLK x 640/656

31,968.78

256

8.0078

3370

105.415

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