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HD66731A01TB0L Datasheet(PDF) 65 Page - Hitachi Semiconductor

Part # HD66731A01TB0L
Description  Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display
PDF  131 Pages
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Manufacturer  HITACHI [Hitachi Semiconductor]
Direct Link  http://www.renesas.com/eng
Logo HITACHI - Hitachi Semiconductor

HD66731A01TB0L Datasheet(HTML) 65 Page - Hitachi Semiconductor

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HD66730/HD66731
64
Relationship between SEGRAM Addresses and Display Patterns
SEGRAM data is displayed when the select level of the COMS pin is output. Since SEGRAM data does
not depend on character code data in DDRAM, and does not undergo horizontal smooth scroll, it can be
used to display icon and marks. The following shows the relationship between SEGRAM addresses and
segment output pins.
Table 8
Relationship between SEGRAM Addresses and Display Patterns
B1
B0
SEG1
SEG7
B1
B0
SEG13
B1
B0
SEG19
B1
B0
SEG25
B1
B0
SEG31
B1
B0
SEG37
B1
B0
SEG43
B1
B0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
A0
A1
A2
D7
D6
D5
SEGRAM
Address
SEGRAM Data
Blinking control
Pattern on/off
0
0
0
0
0
0
0
0
A3
SEG61
B1
B0
SEG67
B1
B0
SEG73
B1
B0
SEG79
B1
B0
SEG85
B1
B0
SEG91
B1
B0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
SEG49
B1
B0
SEG55
SEG2
SEG8
SEG14
SEG20
SEG26
SEG32
SEG38
SEG44
D4
SEG62
SEG68
SEG74
SEG80
SEG86
SEG92
SEG50
SEG56
SEG3
SEG9
SEG15
SEG21
SEG27
SEG33
SEG39
SEG45
D3
SEG63
SEG69
SEG75
SEG81
SEG87
SEG93
SEG51
SEG57
SEG4
SEG10
SEG16
SEG22
SEG28
SEG34
SEG40
SEG46
D2
SEG64
SEG70
SEG76
SEG82
SEG88
SEG94
SEG52
SEG58
SEG5
SEG11
SEG17
SEG23
SEG29
SEG35
SEG41
SEG47
D1
SEG65
SEG71
SEG77
SEG83
SEG89
SEG95
SEG53
SEG59
SEG6
SEG12
SEG18
SEG24
SEG30
SEG36
SEG42
SEG48
D0
SEG66
SEG72
SEG78
SEG84
SEG90
SEG96
SEG54
SEG60
B1
B0
Notes: 1. SEG1 to SEG71 are pin numbers of the segment output driver of the HD66730. Pin SEG1 is
positioned on the left edge of the display. Segments from SEG72 on are displayed by extension
drivers. After SEG 96, display is performed from SEG1 again.
2. The lower six bits (D0 to D5) indicate display on/off for of each segment. A bit setting of 1 selects
display while 0 selects no display.
3. Pattern blinking of the lower six bits is controlled by the upper two bits (D6 and D7) of SEGRAM
data. When the upper two bits (B0 and B1) are 10, segments whose corresponding bits in the
lower 6 bits are set to 1 will blink on the display. When the upper two bits (B0 and B1) are 01,
only the bit-5 pattern can blink. Do not attempt to set the upper two bits (B0 and B1) to 11
(setting is prohibited).



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