AD8315ARMZ datasheet(13/22 Pages) AD

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Data Sheet

AD8315

Rev. D | Page 13 of 22

The intercept need not correspond to a physically realizable

part of the signal range for the log amp. Therefore, the specified

intercept is −70 dBV, at 0.1 GHz, whereas the smallest input for

accurate measurement (a +1 dB error, see Table 2) at this frequency

is higher, being about −58 dBV. At 2.5 GHz, the +1 dB error point

shifts to −64 dBV. This positioning of the intercept is deliberate

and ensures that the VSET voltage is within the capabilities of

certain DACs, whose outputs cannot swing below 200 mV.

Figure 33 shows the 100 MHz response of the AD8315; the

vertical axis does not represent the output (at pin VAPC) but

the value required at the power control pin, VSET, to null the

control loop.

1.5

1.0

0.5

–70dBV

1.416V @ –11dBV

0.288V @ –58dBV

ACTUAL

IDEAL

100µV

–80dBV

–67dBm

1mV

–60dBV

–47dBm

10mV

–40dBV

–27dBm

100mV

–20dBV

–7dBm

1V (RMS)

0dBV

+13dBm (RE 50Ω)

VIN, dBVIN, PIN

Figure 33. Basic Calibration of the AD8315 at 0.1 GHz

CONTROLLER-MODE LOG AMPS

The AD8315 combines the two key functions required for the

measurement and control of the power level over a moderately

wide dynamic range. First, it provides the amplification needed

to respond to small signals in a chain of four amplifier/limiter

cells (see Figure 32), each having a small signal gain of 10 dB and a

bandwidth of approximately 3.5 GHz. At the output of each of

these amplifier stages is a full-wave rectifier, essentially a square

law detector cell that converts the RF signal voltages to a fluctuating

current having an average value that increases with signal level.

A further passive detector stage is added before the first stage.

These five detectors are separated by 10 dB, spanning some 50 dB

of dynamic range. Their outputs are each in the form of a

differential current, making summation a simple matter. It is

readily shown that the summed output can closely approximate

a logarithmic function. The overall accuracy at the extremes of

this total range, viewed as the deviation from an ideal logarithmic

response, that is, the log conformance error, can be judged by

referring to Figure 7, which shows that errors across the central

40 dB are moderate. Other performance curves show how

conformance to an ideal logarithmic function varies with

supply voltage, temperature, and frequency.

In a device intended for measurement applications, this current

is converted to an equivalent voltage, to provide the log (VIN)

function shown in Equation 1. However, the design of the AD8315

differs from standard practice in that the output must be a low

noise control voltage for an RF power amplifier not a direct

measure of the input level. Furthermore, it is highly desirable that

this voltage be proportional to the time integral of the error

between the actual input VIN and the dc voltage VSET (applied to

Pin 3, VSET) that defines the setpoint, that is, a target value for

the power level, typically generated by a DAC.

This is achieved by converting the difference between the sum

of the detector outputs (still in current form) and an internally

generated current proportional to VSET to a single-sided, current-

mode signal. This, in turn, is converted to a voltage (at Pin 4,

FLTR, the low-pass filter capacitor node) to provide a close

approximation to an exact integration of the error between the

power present in the termination at the input of the AD8315

and the setpoint voltage. Finally, the voltage developed across

the ground-referenced filter capacitor CFLT is buffered by a special

low noise amplifier of low voltage gain (×1.35) and presented at

Pin 7 (VAPC) for use as the control voltage for the RF power

amplifier. This buffer can provide rail-to-rail swings and can

drive a substantial load current, including large capacitors. Note

that the RF power amplifier is assumed to have a positive slope

with RF power increasing monotonically with an increasing

APC control voltage.

CONTROL LOOP DYNAMICS

To understand how the AD8315 behaves in a complete control

loop, an expression for the current in the integration capacitor

as a function of the input VIN and the setpoint voltage VSET must

be developed (see Figure 34).

RFIN

FLTR

VAPC

×1.35

ISET = VSET/4.15kΩ

VSET

VIN

IDET = ISLPlog10 (VIN/VZ)

IERR

IDET

CFLT

SETPOINT

INTERFACE

LOGARITHMIC

RF DETECTION

SUBSYSTEM

Figure 34. Behavioral Model of the AD8315

First, the summed detector currents are written as a function of

the input

IDET = ISLP log10 (VIN/VZ)

(3)

where:

IDET is the partially filtered demodulated signal, whose

exact average value is extracted through the subsequent

integration step.

ISLP is the current-mode slope and has a value of 115 μA per

decade (that is, 5.75 μA/dB).

VIN is the input in V rms.

VZ is the effective intercept voltage, which, as previously noted,

is dependent on waveform but is 316 μV rms (−70 dBV) for a

sine wave input.

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