AD8315ARMZ datasheet(14/22 Pages) AD

14 / 22 page

AD8315

Data Sheet

Rev. D | Page 14 of 22

Now the current generated by the setpoint interface is simply

ISET(4) = VSET/415 kΩ

(4)

The difference between this current and IDET is applied to the

loop filter capacitor CFLT. It follows that the voltage appearing

on this capacitor, VFLT, is the time integral of the difference

current:

VFLT(s) = (ISET − IDET)/sCFLT

(5)





FLT

SLP

SET

log

kΩ

4.15





(6)

The control output VAPC is slightly greater than this, because the

gain of the output buffer is ×1.35. In addition, an offset voltage

is deliberately introduced in this stage; this is inconsequential

because the integration function implicitly allows for an arbitrary

constant to be added to the form of Equation 6. The polarity is

such that VAPC rises to the maximum value for any value of VSET

greater than the equivalent value of VIN. In practice, the VAPC

output rails to the positive supply under this condition unless

the control loop through the power amplifier is present. In other

words, the AD8315 seeks to drive the RF power to the maximum

value whenever it falls below the setpoint. The use of exact

integration results in a final error that is theoretically 0, and the

logarithmic detection law ideally results in a constant response

time following a step change of either the setpoint or the power

level, if the power-amplifier control function were likewise linear in

dB. However, this latter condition is rarely true, and it follows that

in practice, the loop response time depends on the power level,

and this effect can strongly influence the design of the control loop.

Equation 6 can be restated as







SLP

SET

APC

log





(7)

where VSLP is the volts-per-decade slope from Equation 1, having a

value of 480 mV/decade, and T is an effective time constant for

the integration, being equal to 4.15 kΩ × CFLT/1.35; the resistor

value comes from the setpoint interface scaling Equation 4 and

the factor 1.35 arises because of the voltage gain of the buffer.

Therefore, the integration time constant can be written as

T = 3.07 CFLT in μs, when C is expressed in nF

(8)

To simplify our understanding of the control loop dynamics,

begin by assuming that the power amplifier gain function is

actually linear in dB, and for the moment, use voltages to

express the signals at the power amplifier input and output.

Let the RF output voltage be VPA and let the input be VCW.

Furthermore, to characterize the gain control function, this

form is used





GBC

APC V



(9)

where:

GO is the gain of the power amplifier when VAPC = 0.

VGBC is the gain scaling.

While few amplifiers conform so conveniently to this law, it

provides a clearer starting point for understanding the more

complex situation that arises when the gain control law is less ideal.

This idealized control loop is shown in Figure 35. With some

manipulation, it is found that the characteristic equation of this

system is

 







GBC

SLP

GBC

SET

APC







log

(10)

where:

k is the coupling factor from the output of the power amplifier

to the input of the AD8315 (for example, ×0.1 for a 20 dB coupler).

TO is a modified time constant (VGBC/VSLP)T.

This is quite easy to interpret. First, it shows that a system of

this sort exhibits a simple single-pole response, for any power

level, with the customary exponential time domain form for

either increasing or decreasing step polarities in the demand

level VSET or the carrier input VCW. Second, it reveals that the

final value of the control voltage VAPC is determined by several

fixed factors:



 







SLP

GBC

SET

APC

log









(11)

Example

Assume that the gain magnitude of the power amplifier runs

from a minimum value of ×0.316 (−10 dB) at VAPC = 0 to ×100

(40 dB) at VAPC = 2.5 V. Applying Equation 9, GO = 0.316 and

VGBC = 1 V. Using a coupling factor of k = 0.0316 (that is, a

30 dB directional coupler) and recalling that the nominal value

of VSLP is 480 mV and VZ = 316 μV for the AD8315, first calculate

the range of values needed for VSET to control an output range of

+33 dBm to −17 dBm. This can be found by noting that, in the

steady state, the numerator of Equation 7 must be 0, that is:

VSET = VSLP log10 (kVPA/VZ)

(12)

where VIN is expanded to kVPA, the fractional voltage sample of

the power amplifier output. For 33 dBm, VPA = 10 V rms, which

evaluates to

VSET (max) = 0.48 log10 (316 mV/316 μV) = 1.44 V

(13)

For a delivered power of −17 dBm, VPA = 31.6 mV rms

VSET (min) = 0.48 log10 (1 mV/316 μV) = 0.24 V

(14)

Check that the power range is 50 dB, which must correspond to

a voltage change in VSET of 50 dB × 24 mV/dB = 1.2 V,

which agrees.

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